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Searched refs:pll_type (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctl_subr.c83 uint8_t pll_type, uint32_t *fixed_hz) in bhnd_pwrctl_si_clkreg_m() argument
85 switch (pll_type) { in bhnd_pwrctl_si_clkreg_m()
106 uint32_t pll_type, uint32_t n, uint32_t m) in bhnd_pwrctl_si_clock_rate() argument
114 if (pll_type == CHIPC_PLL_TYPE3) in bhnd_pwrctl_si_clock_rate()
131 uint8_t pll_type, uint32_t *fixed_hz) in bhnd_pwrctl_cpu_clkreg_m() argument
133 switch (pll_type) { in bhnd_pwrctl_cpu_clkreg_m()
197 switch (pll_type) { in bhnd_pwrctl_clock_rate()
228 if (pll_type == CHIPC_PLL_TYPE3 || pll_type == CHIPC_PLL_TYPE7) { in bhnd_pwrctl_clock_rate()
244 switch (pll_type) { in bhnd_pwrctl_clock_rate()
250 if (pll_type == CHIPC_PLL_TYPE1 || pll_type == CHIPC_PLL_TYPE3) in bhnd_pwrctl_clock_rate()
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H A Dbhnd_pwrctlvar.h40 uint32_t bhnd_pwrctl_clock_rate(uint32_t pll_type, uint32_t n,
44 uint8_t pll_type, uint32_t *fixed_hz);
46 uint32_t pll_type, uint32_t n, uint32_t m);
49 uint8_t pll_type, uint32_t *fixed_hz);
51 uint32_t pll_type, uint32_t n, uint32_t m);
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipc.h77 uint8_t pll_type; /**< PLL type */ member
H A Dchipc_subr.c297 caps->pll_type, CC_TFS(jtag_master)); in chipc_print_caps()
H A Dchipc.c464 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); in chipc_read_caps()
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c49 enum pll_type { enum
104 enum pll_type type;
388 enum pll_type type;
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c52 enum pll_type { enum
131 enum pll_type type;
574 enum pll_type type;