| /netbsd/sys/arch/arm/nxp/ |
| H A D | imx6sx_clk.c | 1068 CLK_MUX("step", step_p, CCM, CCSR, STEP_SEL),
1070 CLK_MUX("ocram_sel", ocram_p, CCM, CBCDR, AXI_SEL),
1077 CLK_MUX("vid_sel", vid_p, CCM, CSCMR2, VID_CLK_SEL),
1081 CLK_MUX("can_sel", can_p, CCM, CSCMR2, CAN_CLK_SEL),
1086 CLK_MUX("m4_sel", m4_p, CCM, CHSCCDR, M4_CLK_SEL),
1087 CLK_MUX("ecspi_sel", ecspi_p, CCM, CSCDR2, ECSPI_SEL),
1098 CLK_MUX("cko1_sel", cko1_p, CCM, CCOSR, CLKO1_SEL),
1099 CLK_MUX("cko2_sel", cko2_p, CCM, CCOSR, CLKO2_SEL),
1100 CLK_MUX("cko", cko_p, CCM, CCOSR, CLK_OUT_SEL),
1104 CLK_MUX("ssi1_sel", ssi_p, CCM, CSCMR1, SSI1_CLK_SEL),
[all …]
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| H A D | imx6_clk.c | 981 CLK_MUX("step", step_p, CCM, CCSR, STEP_SEL),
987 CLK_MUX("axi_sel", axi_p, CCM, CBCDR, AXI_SEL),
993 CLK_MUX("esai_sel", audio_p, CCM, CSCMR2, ESAI_CLK_SEL),
1008 CLK_MUX("cko1_sel", cko1_p, CCM, CCOSR, CLKO1_SEL),
1009 CLK_MUX("cko2_sel", cko2_p, CCM, CCOSR, CLKO2_SEL),
1010 CLK_MUX("cko", cko_p, CCM, CCOSR, CLK_OUT_SEL),
1013 CLK_MUX("ssi1_sel", ssi_p, CCM, CSCMR1, SSI1_CLK_SEL),
1014 CLK_MUX("ssi2_sel", ssi_p, CCM, CSCMR1, SSI2_CLK_SEL),
1015 CLK_MUX("ssi3_sel", ssi_p, CCM, CSCMR1, SSI3_CLK_SEL),
1020 CLK_MUX("eim_sel", eim_p, CCM, CSCMR1, ACLK_SEL),
[all …]
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| H A D | imx6_ccmvar.h | 255 #define CLK_MUX(_name, _parents, _base, _reg, _mask) { \ macro
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| /netbsd/sys/arch/arm/nvidia/ |
| H A D | tegra124_car.c | 491 CLK_MUX("mux_sata_oob",
493 CLK_MUX("mux_sata",
498 CLK_MUX("mux_hda",
503 CLK_MUX("mux_mselect",
506 CLK_MUX("mux_tsensor",
509 CLK_MUX("mux_host1x",
512 CLK_MUX("mux_disp1",
515 CLK_MUX("mux_disp2",
518 CLK_MUX("mux_hdmi",
527 CLK_MUX("mux_xusb_ss",
[all …]
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| H A D | tegra210_car.c | 510 CLK_MUX("MUX_XUSB_HOST",
513 CLK_MUX("MUX_XUSB_FALCON",
516 CLK_MUX("MUX_XUSB_SS",
519 CLK_MUX("MUX_XUSB_FS",
523 CLK_MUX("MUX_MSELECT",
527 CLK_MUX("MUX_TSENSOR",
530 CLK_MUX("MUX_SOC_THERM",
534 CLK_MUX("MUX_HDA2CODEC_2X",
537 CLK_MUX("MUX_HDA",
541 CLK_MUX("MUX_SATA_OOB",
[all …]
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| /netbsd/sys/arch/arm/samsung/ |
| H A D | exynos5410_clock.c | 164 #define CLK_MUX(_name, _reg, _bits, _p) \ macro
275 CLK_MUX("mout_apll", EXYNOS5410_SRC_CPU, __BIT(0), mout_apll_p),
276 CLK_MUX("mout_cpu", EXYNOS5410_SRC_CPU, __BIT(16), mout_cpu_p),
277 CLK_MUX("mout_kpll", EXYNOS5410_SRC_KFC, __BIT(0), mout_kpll_p),
278 CLK_MUX("mout_kfc", EXYNOS5410_SRC_KFC, __BIT(16), mout_kfc_p),
280 CLK_MUX("sclk_mpll", EXYNOS5410_SRC_CPERI1, __BIT(8), mout_mpll_p),
282 CLK_MUX("sclk_bpll", EXYNOS5410_SRC_CDREX, __BIT(0), mout_bpll_p),
284 CLK_MUX("sclk_epll", EXYNOS5410_SRC_TOP2, __BIT(12), mout_epll_p),
285 CLK_MUX("sclk_cpll", EXYNOS5410_SRC_TOP2, __BIT(8), mout_cpll_p),
288 CLK_MUX("mout_mmc0", EXYNOS5410_SRC_FSYS, __BITS(3,0), mout_group2_p),
[all …]
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| H A D | exynos5422_clock.c | 308 #define CLK_MUX(_name, _reg, _bits, _p) \ macro
466 CLK_MUX("mout_aclk66", EXYNOS5422_SRC_TOP1, __BITS(9,8),
473 CLK_MUX("mout_sw_aclk66", EXYNOS5422_SRC_TOP11, __BIT(8),
478 CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4),
480 CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20),
482 CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8),
484 CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12),
486 CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16),
488 CLK_MUX("mout_uart0", EXYNOS5422_SRC_PERIC0, __BITS(6,4),
490 CLK_MUX("mout_uart1", EXYNOS5422_SRC_PERIC0, __BITS(10,8),
[all …]
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