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Searched refs:mmCP_MEC_ME1_UCODE_DATA (Results 1 – 15 of 15) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_psp_v10_0.c277 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v10_0_sram_map()
H A Damdgpu_psp_v12_0.c381 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v12_0_sram_map()
H A Damdgpu_psp_v3_1.c457 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v3_1_sram_map()
H A Damdgpu_psp_v11_0.c610 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); in psp_v11_0_sram_map()
H A Damdgpu_gfx_v7_0.c2755 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_cp_compute_load_microcode()
H A Damdgpu_gfx_v10_0.c2951 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, in gfx_v10_0_cp_compute_load_microcode()
H A Damdgpu_gfx_v9_0.c3294 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, in gfx_v9_0_cp_compute_load_microcode()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h253 #define mmCP_MEC_ME1_UCODE_DATA 0x305d macro
H A Dgfx_7_2_d.h255 #define mmCP_MEC_ME1_UCODE_DATA 0x305d macro
H A Dgfx_8_0_d.h284 #define mmCP_MEC_ME1_UCODE_DATA 0xf81b macro
H A Dgfx_8_1_d.h285 #define mmCP_MEC_ME1_UCODE_DATA 0xf81b macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6744 #define mmCP_MEC_ME1_UCODE_DATA macro
H A Dgc_9_2_1_offset.h6996 #define mmCP_MEC_ME1_UCODE_DATA macro
H A Dgc_9_1_offset.h6968 #define mmCP_MEC_ME1_UCODE_DATA macro
H A Dgc_10_1_0_offset.h10228 #define mmCP_MEC_ME1_UCODE_DATA macro