Searched refs:mmUVD_MPC_SET_MUXB0 (Results 1 – 15 of 15) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_2_d.h | 58 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
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| H A D | uvd_4_0_d.h | 60 #define mmUVD_MPC_SET_MUXB0 0x3D7B macro
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| H A D | uvd_5_0_d.h | 64 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
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| H A D | uvd_6_0_d.h | 80 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
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| H A D | uvd_7_0_offset.h | 170 #define mmUVD_MPC_SET_MUXB0 … macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 352 #define mmUVD_MPC_SET_MUXB0 … macro
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| H A D | vcn_2_5_offset.h | 767 #define mmUVD_MPC_SET_MUXB0 … macro
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| H A D | vcn_2_0_0_offset.h | 602 #define mmUVD_MPC_SET_MUXB0 … macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_uvd_v4_2.c | 300 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v4_2_start()
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| H A D | amdgpu_uvd_v5_0.c | 347 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v5_0_start()
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| H A D | amdgpu_vcn_v2_0.c | 804 UVD, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_0_start_dpg_mode()
928 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v2_0_start()
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| H A D | amdgpu_vcn_v1_0.c | 832 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v1_0_start_spg_mode()
1015 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v1_0_start_dpg_mode()
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| H A D | amdgpu_vcn_v2_5.c | 812 UVD, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_5_start_dpg_mode()
955 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0, in vcn_v2_5_start()
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| H A D | amdgpu_uvd_v6_0.c | 763 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v6_0_start()
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| H A D | amdgpu_uvd_v7_0.c | 1008 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v7_0_start()
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