Home
last modified time | relevance | path

Searched refs:mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL (Results 1 – 12 of 12) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h82 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
H A Duvd_4_0_d.h81 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3 macro
H A Duvd_5_0_d.h88 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
H A Duvd_6_0_d.h104 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
H A Duvd_7_0_offset.h216 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h404 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
H A Dvcn_2_5_offset.h819 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
H A Dvcn_2_0_0_offset.h708 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd_v4_2.c188 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
H A Damdgpu_uvd_v5_0.c185 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init()
H A Damdgpu_uvd_v6_0.c500 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
H A Damdgpu_uvd_v7_0.c568 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); in uvd_v7_0_hw_init()