| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_2_d.h | 68 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_4_0_d.h | 96 #define mmUVD_VCPU_CNTL 0x3D98 macro
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| H A D | uvd_5_0_d.h | 74 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_6_0_d.h | 90 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| H A D | uvd_7_0_offset.h | 190 #define mmUVD_VCPU_CNTL … macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn_v2_5.c | 782 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
842 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
925 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
987 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1007 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1011 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1344 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1349 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
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| H A D | amdgpu_uvd_v4_2.c | 280 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v4_2_start()
431 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v4_2_stop()
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| H A D | amdgpu_uvd_v5_0.c | 357 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v5_0_start()
452 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v5_0_stop()
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| H A D | amdgpu_vcn_v2_0.c | 774 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_0_start_dpg_mode()
899 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), in vcn_v2_0_start()
1108 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, in vcn_v2_0_stop()
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| H A D | amdgpu_vcn_v1_0.c | 850 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()
983 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1143 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, in vcn_v1_0_stop_spg_mode()
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| H A D | amdgpu_uvd_v7_0.c | 888 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in uvd_v7_0_sriov_start()
1019 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, in uvd_v7_0_start()
1146 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); in uvd_v7_0_stop()
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| H A D | amdgpu_uvd_v6_0.c | 773 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
885 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v6_0_stop()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 378 #define mmUVD_VCPU_CNTL … macro
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| H A D | vcn_2_5_offset.h | 731 #define mmUVD_VCPU_CNTL … macro
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| H A D | vcn_2_0_0_offset.h | 660 #define mmUVD_VCPU_CNTL … macro
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