| /netbsd/sys/arch/arm/sunxi/ |
| H A D | sunxi_ccu_fractional.c | 110 u_int parent_rate, best_rate, best_m; in sunxi_ccu_fractional_set_rate() local
121 parent_rate = clk_get_rate(clkp_parent); in sunxi_ccu_fractional_set_rate()
122 if (parent_rate == 0) in sunxi_ccu_fractional_set_rate()
133 parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1); in sunxi_ccu_fractional_set_rate()
135 parent_rate = parent_rate / fractional->prediv_val; in sunxi_ccu_fractional_set_rate()
156 rate = parent_rate * m; in sunxi_ccu_fractional_set_rate()
189 u_int parent_rate, best_rate; in sunxi_ccu_fractional_round_rate() local
201 if (parent_rate == 0) in sunxi_ccu_fractional_round_rate()
207 parent_rate = parent_rate / fractional->prediv_val; in sunxi_ccu_fractional_round_rate()
210 parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1); in sunxi_ccu_fractional_round_rate()
[all …]
|
| H A D | sunxi_ccu_display.c | 105 int parent_rate, best_parent_rate; in sunxi_ccu_lcdxch1_set_rate() local
115 parent_rate = clk_round_rate(pllclkp, in sunxi_ccu_lcdxch1_set_rate()
117 if (parent_rate == 0) in sunxi_ccu_lcdxch1_set_rate()
119 rate = parent_rate * d / m; in sunxi_ccu_lcdxch1_set_rate()
125 best_parent_rate = parent_rate; in sunxi_ccu_lcdxch1_set_rate()
|
| H A D | sunxi_twi.c | 85 sunxi_twi_calc_rate(u_int parent_rate, u_int n, u_int m) in sunxi_twi_calc_rate() argument
87 return parent_rate / (10 * (m + 1) * (1 << n)); in sunxi_twi_calc_rate()
91 sunxi_twi_set_clock(struct gttwsi_softc *sc, u_int parent_rate, u_int rate) in sunxi_twi_set_clock() argument
101 sunxi_twi_calc_rate(parent_rate, n, m); in sunxi_twi_set_clock()
|
| H A D | sunxi_ccu_nm.c | 107 u_int parent_rate, best_rate, best_n, best_m, best_parent; in sunxi_ccu_nm_set_rate() local
138 parent_rate = clk_get_rate(clkp_parent); in sunxi_ccu_nm_set_rate()
139 if (parent_rate == 0) in sunxi_ccu_nm_set_rate()
145 rate = parent_rate / (1 << n) / (m + 1); in sunxi_ccu_nm_set_rate()
147 rate = parent_rate / (n + 1) / (m + 1); in sunxi_ccu_nm_set_rate()
|
| H A D | sunxi_ccu_div.c | 139 int parent_rate; in sunxi_ccu_div_set_rate() local
159 parent_rate = clk_get_rate(clkp_parent); in sunxi_ccu_div_set_rate()
160 if (parent_rate == 0) in sunxi_ccu_div_set_rate()
163 ratio = howmany(parent_rate, new_rate); in sunxi_ccu_div_set_rate()
|
| H A D | sunxi_rtc.c | 525 u_int parent_rate = clk_get_rate(sc->sc_parent_clk); in sunxi_rtc_clk_get_rate() local
529 return parent_rate; in sunxi_rtc_clk_get_rate()
532 parent_rate /= sc->sc_conf->fixed_prescaler; in sunxi_rtc_clk_get_rate()
540 return parent_rate / (prescaler + 1); in sunxi_rtc_clk_get_rate()
|
| H A D | sunxi_hdmi.c | 848 int parent_rate; in sunxi_hdmi_set_videomode() local
875 parent_rate = clk_get_rate(clk_pll); in sunxi_hdmi_set_videomode()
876 KASSERT(parent_rate > 0); in sunxi_hdmi_set_videomode()
881 int cur_rate = parent_rate / m / d; in sunxi_hdmi_set_videomode()
892 device_printf(sc->sc_dev, "parent rate: %d\n", parent_rate); in sunxi_hdmi_set_videomode()
|
| H A D | sunxi_hdmiphy.c | 374 const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0); in sunxi_hdmiphy_set_rate() local
379 const u_int tmp_rate = parent_rate / (prediv + 1); in sunxi_hdmiphy_set_rate()
|
| /netbsd/sys/arch/arm/amlogic/ |
| H A D | meson_clk_pll.c | 46 uint64_t parent_rate, rate; in meson_clk_pll_get_rate() local
56 parent_rate = clk_get_rate(clkp_parent); in meson_clk_pll_get_rate()
57 if (parent_rate == 0) in meson_clk_pll_get_rate()
77 rate = parent_rate * m; in meson_clk_pll_get_rate()
79 uint64_t frac_rate = parent_rate * frac; in meson_clk_pll_get_rate()
104 uint64_t parent_rate, tmp; in meson_clk_pll_set_rate() local
118 parent_rate = clk_get_rate(clkp_parent); in meson_clk_pll_set_rate()
119 if (parent_rate == 0) { in meson_clk_pll_set_rate()
124 if (parent_rate > new_rate) { in meson_clk_pll_set_rate()
125 n = parent_rate / new_rate; in meson_clk_pll_set_rate()
[all …]
|
| H A D | meson_clk_mpll.c | 47 uint64_t parent_rate, sdm, n2; in meson_clk_mpll_get_rate() local
57 parent_rate = clk_get_rate(clkp_parent); in meson_clk_mpll_get_rate()
58 if (parent_rate == 0) in meson_clk_mpll_get_rate()
75 return (u_int)howmany(parent_rate * SDM_DEN, div); in meson_clk_mpll_get_rate()
|
| H A D | meson_clk_div.c | 85 int parent_rate; in meson_clk_div_set_rate() local
106 parent_rate = clk_get_rate(clkp_parent); in meson_clk_div_set_rate()
107 if (parent_rate == 0) { in meson_clk_div_set_rate()
112 ratio = howmany(parent_rate, new_rate); in meson_clk_div_set_rate()
|
| H A D | meson8b_clkc.c | 116 const u_int parent_rate = clk_get_rate(clkp_parent); in meson8b_clkc_pll_sys_set_rate() local
117 if (parent_rate == 0) in meson8b_clkc_pll_sys_set_rate()
125 u_int new_mul = rate / parent_rate; in meson8b_clkc_pll_sys_set_rate()
161 delay((100 * old_rate) / parent_rate); in meson8b_clkc_pll_sys_set_rate()
|
| H A D | mesongx_mmc.c | 482 const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]); in mesongx_mmc_set_clock() local
484 const u_int rate = parent_rate / div; in mesongx_mmc_set_clock()
|
| /netbsd/sys/arch/arm/ti/ |
| H A D | ti_dpll_clock.c | 226 uint64_t parent_rate; in ti_dpll_clock_get_rate() local
235 parent_rate = clk_get_rate(clk_parent); in ti_dpll_clock_get_rate()
237 return (u_int)((mult * parent_rate) / div); in ti_dpll_clock_get_rate()
254 uint64_t parent_rate; in am3_dpll_clock_set_rate() local
260 parent_rate = clk_get_rate(clk_parent); in am3_dpll_clock_set_rate()
261 if (parent_rate == 0) in am3_dpll_clock_set_rate()
264 const u_int div = (parent_rate / 1000000) - 1; in am3_dpll_clock_set_rate()
296 uint64_t parent_rate; in omap3_dpll_clock_set_rate() local
302 parent_rate = clk_get_rate(clk_parent); in omap3_dpll_clock_set_rate()
336 uint64_t parent_rate; in omap3_dpll_core_clock_get_rate() local
[all …]
|
| H A D | ti_div_clock.c | 158 uint64_t parent_rate; in ti_div_clock_get_rate() local
191 parent_rate = clk_get_rate(clk_parent); in ti_div_clock_get_rate()
193 return (u_int)(parent_rate / div); in ti_div_clock_get_rate()
|
| /netbsd/sys/arch/arm/altera/ |
| H A D | cycv_clkmgr.c | 457 uint32_t parent_rate = 0; in cycv_clkmgr_clock_get_rate() local
472 parent_rate = cycv_clkmgr_clock_get_rate(priv, &parent->base); in cycv_clkmgr_clock_get_rate()
475 parent_rate /= 2; in cycv_clkmgr_clock_get_rate()
477 parent_rate /= 4; in cycv_clkmgr_clock_get_rate()
479 parent_rate /= 4; in cycv_clkmgr_clock_get_rate()
483 return parent_rate / clk->u.fixed_div; in cycv_clkmgr_clock_get_rate()
494 return parent_rate / divisor; in cycv_clkmgr_clock_get_rate()
501 return (uint64_t) parent_rate * numer / divisor; in cycv_clkmgr_clock_get_rate()
|
| /netbsd/sys/arch/arm/nvidia/ |
| H A D | tegra124_car.c | 1218 return parent_rate / tfixed_div->div; in tegra124_car_clock_get_rate_fixed_div()
1256 rate = parent_rate * 1 / (raw_div + 1); in tegra124_car_clock_get_rate_div()
1264 parent_rate, raw_div); in tegra124_car_clock_get_rate_div()
1266 rate = parent_rate; in tegra124_car_clock_get_rate_div()
1270 rate = tegra124_car_clock_calc_rate_frac_div(parent_rate, in tegra124_car_clock_get_rate_div()
1305 if (rate == parent_rate) { in tegra124_car_clock_set_rate_div()
1309 raw_div = (parent_rate * 2) / rate - 2; in tegra124_car_clock_set_rate_div()
1317 raw_div = (parent_rate * 2) / rate - 2; in tegra124_car_clock_set_rate_div()
1329 raw_div = parent_rate / rate - 1; in tegra124_car_clock_set_rate_div()
1339 parent_rate, raw_div); in tegra124_car_clock_set_rate_div()
[all …]
|
| H A D | tegra210_car.c | 1322 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); in tegra210_car_clock_get_rate_fixed_div() local
1324 return parent_rate / tfixed_div->div; in tegra210_car_clock_get_rate_fixed_div()
1352 rate = parent_rate / (raw_div + 1); in tegra210_car_clock_get_rate_div()
1359 rate = parent_rate / ((raw_div / 2) + 1); in tegra210_car_clock_get_rate_div()
1361 rate = parent_rate; in tegra210_car_clock_get_rate_div()
1375 rate = parent_rate / ((raw_div / 2) + 1); in tegra210_car_clock_get_rate_div()
1409 if (rate == parent_rate) { in tegra210_car_clock_set_rate_div()
1413 raw_div = (parent_rate / rate) * 2; in tegra210_car_clock_set_rate_div()
1425 raw_div = (parent_rate / rate) - 1; in tegra210_car_clock_set_rate_div()
1434 parent_rate / ((raw_div / 2) + 1); in tegra210_car_clock_set_rate_div()
[all …]
|
| H A D | tegra_drm_mode.c | 638 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent); in tegra_crtc_mode_set() local
639 const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2; in tegra_crtc_mode_set()
|
| /netbsd/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nouveau_nvkm_subdev_clk_gk20a.c | 99 rate = clk->parent_rate * pll->n; in gk20a_pllg_calc_rate()
119 ref_clk_f = clk->parent_rate / KHZ; in gk20a_pllg_calc_mnp()
518 switch (clk->parent_rate) { in gk20a_clk_setup_slide()
535 clk->parent_rate / KHZ); in gk20a_clk_setup_slide()
634 clk->parent_rate = clk_get_rate(tdev->clk); in gk20a_clk_ctor()
641 clk->parent_rate / KHZ); in gk20a_clk_ctor()
|
| H A D | gk20a.h | 122 u32 parent_rate; member
148 clk->parent_rate / KHZ); in gk20a_pllg_n_lo()
|
| H A D | nouveau_nvkm_subdev_clk_gm20b.c | 496 u32 parent_rate = clk->base.parent_rate / KHZ; in gm20b_dvfs_calc_safe_pll() local
506 nmin = DIV_ROUND_UP(pll->m * clk->base.params->min_vco, parent_rate); in gm20b_dvfs_calc_safe_pll()
507 nsafe = pll->m * rate / (clk->base.parent_rate); in gm20b_dvfs_calc_safe_pll()
510 pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate); in gm20b_dvfs_calc_safe_pll()
1054 (clk->base.parent_rate / KHZ)); in gm20b_clk_new()
|
| /netbsd/sys/arch/arm/samsung/ |
| H A D | exynos5422_clock.c | 832 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); in exynos5422_clock_get_rate_div() local
837 return parent_rate / (div + 1); in exynos5422_clock_get_rate_div()
852 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); in exynos5422_clock_set_rate_div() local
855 tmp_rate = parent_rate / (tmp_div + 1); in exynos5422_clock_set_rate_div()
|
| H A D | exynos5410_clock.c | 655 const u_int parent_rate = exynos5410_clock_get_rate(sc, clk_parent); in exynos5410_clock_get_rate_div() local
660 return parent_rate / (div + 1); in exynos5410_clock_get_rate_div()
675 const u_int parent_rate = exynos5410_clock_get_rate(sc, clk_parent); in exynos5410_clock_set_rate_div() local
678 tmp_rate = parent_rate / (tmp_div + 1); in exynos5410_clock_set_rate_div()
|
| /netbsd/sys/arch/arm/rockchip/ |
| H A D | rk_cru_arm.c | 96 const u_int parent_rate = arm_rate->rate / arm_rate->div; in rk_cru_arm_set_rate_rates() local
98 error = clk_set_rate(&main_parent->base, parent_rate); in rk_cru_arm_set_rate_rates()
|