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Searched refs:ixSQ_WAVE_TTMP0 (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h95 #define ixSQ_WAVE_TTMP0 0x0270 macro
H A Dgfx_7_0_d.h1925 #define ixSQ_WAVE_TTMP0 0x270 macro
H A Dgfx_7_2_d.h1946 #define ixSQ_WAVE_TTMP0 0x270 macro
H A Dgfx_8_0_d.h2145 #define ixSQ_WAVE_TTMP0 0x270 macro
H A Dgfx_8_1_d.h2113 #define ixSQ_WAVE_TTMP0 0x270 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7111 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_9_2_1_offset.h7358 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_9_4_2_offset.h7659 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_9_1_offset.h7319 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_9_4_3_offset.h7421 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_10_1_0_offset.h11194 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_11_0_0_offset.h11655 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_11_0_3_offset.h12072 #define ixSQ_WAVE_TTMP0 … macro
H A Dgc_10_3_0_offset.h13443 #define ixSQ_WAVE_TTMP0 … macro