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Searched refs:mmGRBM_GFX_CNTL (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h74 #define mmGRBM_GFX_CNTL … macro
H A Dgc_9_0_offset.h83 #define mmGRBM_GFX_CNTL … macro
H A Dgc_9_2_1_offset.h81 #define mmGRBM_GFX_CNTL … macro
H A Dgc_9_1_offset.h83 #define mmGRBM_GFX_CNTL … macro
H A Dgc_10_1_0_offset.h2089 #define mmGRBM_GFX_CNTL … macro
H A Dgc_10_3_0_offset.h2166 #define mmGRBM_GFX_CNTL … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dnv.c327 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); in nv_grbm_select()
H A Dsoc15.c348 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); in soc15_grbm_select()
H A Dgfx_v10_0.c4140 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_init_rlcg_reg_access_ctrl()
6031 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_cp_gfx_switch_pipe()
6034 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); in gfx_v10_0_cp_gfx_switch_pipe()
H A Dgfx_v9_0.c1642 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v9_0_init_rlcg_reg_access_ctrl()