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Searched refs:mmRLC_CGCG_CGLS_CTRL_3D (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v9_0.c4771 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v9_0_update_3d_clock_gating()
4783 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v9_0_update_3d_clock_gating()
4793 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v9_0_update_3d_clock_gating()
4799 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v9_0_update_3d_clock_gating()
5061 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v10_0.c7619 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v10_0_update_3d_clock_gating()
7631 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v10_0_update_3d_clock_gating()
7641 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); in gfx_v10_0_update_3d_clock_gating()
7652 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v10_0_update_3d_clock_gating()
8125 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); in gfx_v10_0_get_clockgating_state()
H A Dgfx_v8_0.c319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h1394 #define mmRLC_CGCG_CGLS_CTRL_3D 0xec9d macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6253 #define mmRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_9_2_1_offset.h6451 #define mmRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_9_1_offset.h6475 #define mmRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_10_1_0_offset.h9579 #define mmRLC_CGCG_CGLS_CTRL_3D … macro
H A Dgc_10_3_0_offset.h9425 #define mmRLC_CGCG_CGLS_CTRL_3D … macro