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Searched refs:mmSPI_WCL_PIPE_PERCENT_CS3 (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1415 #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc macro
H A Dgfx_7_2_d.h1432 #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc macro
H A Dgfx_8_0_d.h1611 #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc macro
H A Dgfx_8_1_d.h1579 #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2705 #define mmSPI_WCL_PIPE_PERCENT_CS3 … macro
H A Dgc_9_2_1_offset.h2891 #define mmSPI_WCL_PIPE_PERCENT_CS3 … macro
H A Dgc_9_1_offset.h2949 #define mmSPI_WCL_PIPE_PERCENT_CS3 … macro
H A Dgc_10_1_0_offset.h5187 #define mmSPI_WCL_PIPE_PERCENT_CS3 … macro
H A Dgc_10_3_0_offset.h4854 #define mmSPI_WCL_PIPE_PERCENT_CS3 … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v8_0.c6836 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3; in gfx_v8_0_emit_wave_limit_cs()
H A Dgfx_v9_0.c6810 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_0_emit_wave_limit_cs()