/qemu/tests/qtest/ |
H A D | tpm-crb-test.c | 43 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapFIFO), ==, 0); in tpm_crb_test() 44 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRB), ==, 1); in tpm_crb_test() 46 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, RID), ==, 0); in tpm_crb_test() 64 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 1); in tpm_crb_test() 65 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); in tpm_crb_test() 88 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); in tpm_crb_test() 89 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); in tpm_crb_test() 107 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmIdle), ==, 0); in tpm_crb_test() 108 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); in tpm_crb_test() 120 g_assert_cmpint(FIELD_EX32(sts, CRB_CTRL_STS, tpmSts), ==, 0); in tpm_crb_test() [all …]
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H A D | sifive-e-aon-watchdog-test.c | 236 g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_watchdog() 244 g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_watchdog() 278 g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_scaled_watchdog() 286 g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_scaled_watchdog() 319 g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_periodic_int() 325 g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_periodic_int() 338 g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_periodic_int() 344 g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_periodic_int() 377 g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_enable_disable() 395 g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0)); in test_enable_disable() [all …]
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H A D | ufs-test.c | 273 hce = FIELD_EX32(ufs_rreg(ufs, A_HCE), HCE, HCE); in ufs_init() 286 g_assert_true(FIELD_EX32(hcs, HCS, UCRDY)); in ufs_init() 294 g_assert_true(FIELD_EX32(is, IS, UCCS)); in ufs_init() 302 g_assert_true(FIELD_EX32(hcs, HCS, DP)); in ufs_init() 303 g_assert_true(FIELD_EX32(hcs, HCS, UTRLRDY)); in ufs_init() 304 g_assert_true(FIELD_EX32(hcs, HCS, UTMRLRDY)); in ufs_init() 305 g_assert_true(FIELD_EX32(hcs, HCS, UCRDY)); in ufs_init() 324 nutrs = FIELD_EX32(cap, CAP, NUTRS) + 1; in ufs_init() 325 nutmrs = FIELD_EX32(cap, CAP, NUTMRS) + 1; in ufs_init() 408 g_assert_cmpuint(FIELD_EX32(cap, CAP, NUTRS), ==, 31); in ufstest_reg_read() [all …]
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/qemu/target/arm/ |
H A D | cpu-features.h | 72 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; in isar_feature_aa32_pmull() 172 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; in isar_feature_aa32_mve() 183 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; in isar_feature_aa32_mve_fp() 192 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; in isar_feature_aa32_vfp_simd() 203 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; in isar_feature_aa32_fpshvec() 209 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; in isar_feature_aa32_fpsp_v2() 215 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; in isar_feature_aa32_fpsp_v3() 221 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; in isar_feature_aa32_fpdp_v2() 227 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; in isar_feature_aa32_fpdp_v3() 242 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; in isar_feature_aa32_fp16_spconv() [all …]
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/qemu/hw/ssi/ |
H A D | ibex_spi_host.c | 190 if (FIELD_EX32(intr_test_reg, INTR_TEST, ERROR)) { in ibex_spi_host_irq() 360 if (FIELD_EX32(val32, INTR_STATE, ERROR)) { in ibex_spi_host_write() 363 if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { in ibex_spi_host_write() 415 if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL], in ibex_spi_host_write() 421 if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS], in ibex_spi_host_write() 488 txqd_len = FIELD_EX32(status, STATUS, TXQD); in ibex_spi_host_write() 513 if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { in ibex_spi_host_write() 516 if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { in ibex_spi_host_write() 519 if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { in ibex_spi_host_write() 522 if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { in ibex_spi_host_write() [all …]
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/qemu/target/loongarch/ |
H A D | translate.h | 18 #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \ 20 #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP)) 21 #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) 22 #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) 23 #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) 24 #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM)) 25 #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX)) 26 #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX)) 27 #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
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/qemu/hw/misc/ |
H A D | sifive_e_aon.c | 51 if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS) == 0 && in sifive_e_aon_wdt_update_wdogcount() 52 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE) == 0) { in sifive_e_aon_wdt_update_wdogcount() 71 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, SCALE)); in sifive_e_aon_wdt_update_state() 75 if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, ZEROCMP) == 1) { in sifive_e_aon_wdt_update_state() 82 if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, RSTEN) == 1) { in sifive_e_aon_wdt_update_state() 91 (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS) == 1 || in sifive_e_aon_wdt_update_state() 92 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE) == 1)) { in sifive_e_aon_wdt_update_state() 95 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, SCALE), in sifive_e_aon_wdt_update_state() 126 FIELD_EX32(r->wdogcfg, in sifive_e_aon_wdt_read() 160 new_en_always = FIELD_EX32(value, AON_WDT_WDOGCFG, EN_ALWAYS); in sifive_e_aon_wdt_write() [all …]
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H A D | stm32l4x5_rcc.c | 425 val = FIELD_EX32(s->cr, CR, PLLSAI2ON); in rcc_update_cr_register() 434 val = FIELD_EX32(s->cr, CR, PLLSAI1ON); in rcc_update_cr_register() 446 val = FIELD_EX32(s->cr, CR, PLLON); in rcc_update_cr_register() 466 val = FIELD_EX32(s->cr, CR, HSEON); in rcc_update_cr_register() 499 val = FIELD_EX32(s->cr, CR, HSION); in rcc_update_cr_register() 585 val = FIELD_EX32(s->cfgr, CFGR, HPRE); in rcc_update_cfgr_register() 595 val = FIELD_EX32(s->cfgr, CFGR, SW); in rcc_update_cfgr_register() 763 val = FIELD_EX32(reg, PLLCFGR, PLLR); in rcc_update_pllsaixcfgr() 772 val = FIELD_EX32(reg, PLLCFGR, PLLQ); in rcc_update_pllsaixcfgr() 785 val = FIELD_EX32(reg, PLLCFGR, PLLN); in rcc_update_pllsaixcfgr() [all …]
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H A D | xlnx-versal-trng.c | 317 if (FIELD_EX32(st, STATUS, CERTF) && FIELD_EX32(en, INT_CTRL, CERTF_EN)) { in trng_core_int_update() 321 if (FIELD_EX32(st, STATUS, DTF) && FIELD_EX32(en, INT_CTRL, DTF_EN)) { in trng_core_int_update() 325 if (FIELD_EX32(st, STATUS, DONE) && FIELD_EX32(en, INT_CTRL, DONE_EN)) { in trng_core_int_update() 342 if (FIELD_EX32(v32, INT_CTRL, DTF_RST)) { in trng_int_ctrl_postw() 345 if (FIELD_EX32(v32, INT_CTRL, DONE_RST)) { in trng_int_ctrl_postw() 368 if (FIELD_EX32(events, STATUS, CERTF)) { in trng_fault_event_set() 379 if (FIELD_EX32(events, STATUS, DTF)) { in trng_fault_event_set() 405 if (FIELD_EX32(val64, CTRL, PRNGSRST)) { in trng_ctrl_postw() 411 if (!FIELD_EX32(val64, CTRL, PRNGSTART)) { in trng_ctrl_postw() 415 if (FIELD_EX32(val64, CTRL, PRNGMODE)) { in trng_ctrl_postw() [all …]
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H A D | imx6ul_ccm.c | 308 if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS], in imx6ul_analog_get_pll2_clk() 334 / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528], in imx6ul_analog_get_pll2_pfd0_clk() 347 / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528], in imx6ul_analog_get_pll2_pfd2_clk() 368 switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) { in imx6ul_ccm_get_periph_clk2_sel_clk() 398 switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) { in imx6ul_ccm_get_periph_clk_sel_clk() 425 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF)); in imx6ul_ccm_get_periph_clk2_clk() 436 switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) { in imx6ul_ccm_get_periph_sel_clk() 457 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF)); in imx6ul_ccm_get_ahb_clk() 469 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF)); in imx6ul_ccm_get_ipg_clk() 480 switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) { in imx6ul_ccm_get_per_sel_clk() [all …]
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H A D | bcm2835_cprman.c | 69 return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) in pll_is_locked() 70 && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); in pll_is_locked() 82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); in pll_update() 89 ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); in pll_update() 90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); in pll_update() 181 div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); in pll_channel_update() 259 return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE); in clock_mux_is_enabled() 265 uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC); in clock_mux_update() 314 if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) { in clock_mux_src_update() 380 bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD); in dsi0hsck_mux_update() [all …]
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H A D | imx7_src.c | 187 if (FIELD_EX32(change_mask, CORE0, RST)) { in imx7_src_write() 191 if (FIELD_EX32(change_mask, CORE1, RST)) { in imx7_src_write() 207 if (FIELD_EX32(change_mask, CORE1, ENABLE)) { in imx7_src_write() 208 if (FIELD_EX32(current_value, CORE1, ENABLE)) { in imx7_src_write()
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/qemu/target/rx/ |
H A D | helper.c | 29 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); in rx_cpu_unpack_psw() 32 env->psw_pm = FIELD_EX32(psw, PSW, PM); in rx_cpu_unpack_psw() 34 env->psw_u = FIELD_EX32(psw, PSW, U); in rx_cpu_unpack_psw() 35 env->psw_i = FIELD_EX32(psw, PSW, I); in rx_cpu_unpack_psw() 37 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; in rx_cpu_unpack_psw() 38 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; in rx_cpu_unpack_psw() 39 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); in rx_cpu_unpack_psw() 40 env->psw_c = FIELD_EX32(psw, PSW, C); in rx_cpu_unpack_psw()
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/qemu/hw/rtc/ |
H A D | ls7a_rtc.c | 102 return FIELD_EX32(s->cntrctl, RTC_CTRL, TOYEN) && in toy_enabled() 103 FIELD_EX32(s->cntrctl, RTC_CTRL, EO); in toy_enabled() 108 return FIELD_EX32(s->cntrctl, RTC_CTRL, RTCEN) && in rtc_enabled() 109 FIELD_EX32(s->cntrctl, RTC_CTRL, EO); in rtc_enabled() 128 tm->tm_sec = FIELD_EX32(val, TOY_MATCH, SEC); in toymatch_val_to_time() 129 tm->tm_min = FIELD_EX32(val, TOY_MATCH, MIN); in toymatch_val_to_time() 130 tm->tm_hour = FIELD_EX32(val, TOY_MATCH, HOUR); in toymatch_val_to_time() 131 tm->tm_mday = FIELD_EX32(val, TOY_MATCH, DAY); in toymatch_val_to_time() 286 tm.tm_sec = FIELD_EX32(val, TOY, SEC); in ls7a_rtc_write() 287 tm.tm_min = FIELD_EX32(val, TOY, MIN); in ls7a_rtc_write() [all …]
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/qemu/hw/net/ |
H A D | cadence_gem.c | 560 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { in gem_get_max_buf_len() 570 size = FIELD_EX32(s->regs[R_NWCFG], in gem_get_max_buf_len() 811 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { in gem_mac_address_filter() 1105 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { in gem_receive() 1529 phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR); in gem_handle_phy_access() 1533 if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) { in gem_handle_phy_access() 1539 reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR); in gem_handle_phy_access() 1541 switch (FIELD_EX32(val, PHYMNTNC, OP)) { in gem_handle_phy_access() 1617 if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { in gem_write() 1622 if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { in gem_write() [all …]
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/qemu/linux-user/arm/ |
H A D | target_proc.h | 26 midr_rev = FIELD_EX32(cpu->midr, MIDR_EL1, REVISION); in open_cpuinfo() 27 midr_part = FIELD_EX32(cpu->midr, MIDR_EL1, PARTNUM); in open_cpuinfo() 28 midr_var = FIELD_EX32(cpu->midr, MIDR_EL1, VARIANT); in open_cpuinfo() 29 midr_impl = FIELD_EX32(cpu->midr, MIDR_EL1, IMPLEMENTER); in open_cpuinfo()
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/qemu/hw/intc/ |
H A D | gic_internal.h | 135 #define GICH_LR_VIRT_ID(entry) (FIELD_EX32(entry, GICH_LR0, VirtualID)) 136 #define GICH_LR_PHYS_ID(entry) (FIELD_EX32(entry, GICH_LR0, PhysicalID)) 137 #define GICH_LR_CPUID(entry) (FIELD_EX32(entry, GICH_LR0, CPUID)) 138 #define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI)) 139 #define GICH_LR_PRIORITY(entry) (FIELD_EX32(entry, GICH_LR0, Priority) << 3) 140 #define GICH_LR_STATE(entry) (FIELD_EX32(entry, GICH_LR0, State)) 141 #define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1)) 142 #define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW))
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/qemu/target/riscv/ |
H A D | vector_internals.h | 36 return FIELD_EX32(simd_data(desc), VDATA, NF); in vext_nf() 73 return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); in vext_lmul() 78 return FIELD_EX32(simd_data(desc), VDATA, VM); in vext_vm() 83 return FIELD_EX32(simd_data(desc), VDATA, VMA); in vext_vma() 88 return FIELD_EX32(simd_data(desc), VDATA, VTA); in vext_vta() 93 return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); in vext_vta_all_1s()
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H A D | translate.c | 1181 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); in riscv_tr_init_disas_context() 1182 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); in riscv_tr_init_disas_context() 1183 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); in riscv_tr_init_disas_context() 1184 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); in riscv_tr_init_disas_context() 1186 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); in riscv_tr_init_disas_context() 1190 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); in riscv_tr_init_disas_context() 1191 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); in riscv_tr_init_disas_context() 1197 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); in riscv_tr_init_disas_context() 1199 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); in riscv_tr_init_disas_context() 1200 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); in riscv_tr_init_disas_context() [all …]
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/qemu/hw/char/ |
H A D | stm32l4x5_usart.c | 201 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); in stm32l4x5_usart_base_receive() 292 switch (FIELD_EX32(s->cr2, CR2, STOP)) { in stm32l4x5_update_params() 302 FIELD_EX32(s->cr2, CR2, STOP)); in stm32l4x5_update_params() 307 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { in stm32l4x5_update_params() 324 value = FIELD_EX32(s->brr, BRR, BRR); in stm32l4x5_update_params() 331 if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { in stm32l4x5_update_params() 408 retvalue = FIELD_EX32(s->brr, BRR, BRR); in stm32l4x5_usart_base_read() 428 retvalue = FIELD_EX32(s->rdr, RDR, RDR); in stm32l4x5_usart_base_read() 434 retvalue = FIELD_EX32(s->tdr, TDR, TDR); in stm32l4x5_usart_base_read()
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/qemu/target/arm/tcg/ |
H A D | mte_helper.c | 590 is_write = FIELD_EX32(desc, MTEDESC, WRITE); in mte_sync_check_fail() 624 int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in mte_check_fail() 667 if (FIELD_EX32(desc, MTEDESC, WRITE)) { in mte_check_fail() 823 mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in mte_probe_int() 825 sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1); in mte_probe_int() 980 mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in HELPER() 1051 bool w = FIELD_EX32(desc, MTEDESC, WRITE); in mte_mops_probe() 1054 mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in mte_mops_probe() 1101 bool w = FIELD_EX32(desc, MTEDESC, WRITE); in mte_mops_probe_rev() 1104 mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in mte_mops_probe_rev() [all …]
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/qemu/hw/arm/ |
H A D | raspi.c | 77 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ in board_ram_size() 78 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); in board_ram_size() 83 int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); in board_processor_id() 85 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ in board_processor_id() 107 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ in board_type() 108 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); in board_type() 323 FIELD_EX32(board_rev, REV_CODE, REVISION)); in raspi_machine_class_common_init()
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/qemu/hw/gpio/ |
H A D | aspeed_gpio.c | 631 uint32_t reg_idx_number = FIELD_EX32(data, GPIO_INDEX_REG, NUMBER); in aspeed_gpio_write_index_mode() 632 uint32_t reg_idx_type = FIELD_EX32(data, GPIO_INDEX_REG, TYPE); in aspeed_gpio_write_index_mode() 633 uint32_t reg_idx_command = FIELD_EX32(data, GPIO_INDEX_REG, COMMAND); in aspeed_gpio_write_index_mode() 652 FIELD_EX32(data, GPIO_INDEX_REG, DATA_VALUE)); in aspeed_gpio_write_index_mode() 662 FIELD_EX32(data, GPIO_INDEX_REG, DIRECTION)); in aspeed_gpio_write_index_mode() 682 FIELD_EX32(data, GPIO_INDEX_REG, INT_ENABLE)); in aspeed_gpio_write_index_mode() 687 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_0)); in aspeed_gpio_write_index_mode() 692 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_1)); in aspeed_gpio_write_index_mode() 697 FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2)); in aspeed_gpio_write_index_mode() 703 FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)); in aspeed_gpio_write_index_mode() [all …]
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/qemu/hw/net/can/ |
H A D | xlnx-zynqmp-can.c | 391 frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC); in generate_frame() 393 frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3); in generate_frame() 394 frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2); in generate_frame() 395 frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1); in generate_frame() 396 frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0); in generate_frame() 398 frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7); in generate_frame() 399 frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6); in generate_frame() 400 frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5); in generate_frame() 549 if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) { in can_srr_pre_write() 610 if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { in can_msr_pre_write() [all …]
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H A D | xlnx-versal-canfd.c | 826 multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) + in canfd_msr_pre_write() 827 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) + in canfd_msr_pre_write() 828 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP); in canfd_msr_pre_write() 844 if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { in canfd_msr_pre_write() 878 dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC); in regs2frame() 882 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) { in regs2frame() 1418 if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) { in canfd_srr_pre_write() 1520 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI)) { in canfd_rx_fifo_status_prew() 1522 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) != 0) { in canfd_rx_fifo_status_prew() 1536 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI_1)) { in canfd_rx_fifo_status_prew() [all …]
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