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Searched refs:IMR (Results 1 – 4 of 4) sorted by relevance

/qemu/include/hw/misc/
H A Dxlnx-zynqmp-apu-ctrl.h25 REG32(IMR, 0x14)
26 FIELD(IMR, INV_APB, 0, 1)
/qemu/hw/display/
H A Dtc6393xb.c95 uint8_t IMR; member
190 qemu_set_irq(s->irq, isr & s->scr.IMR); in tc6393xb_sub_irq()
216 SCR_REG_B(IMR); in tc6393xb_scr_readb()
273 SCR_REG_B(IMR); in tc6393xb_scr_writeb()
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c680 REG32(IMR, 0x804)
681 FIELD(IMR, ADDR_DECODE_ERR, 0, 1)
/qemu/hw/net/
H A Dcadence_gem.c194 REG32(IMR, 0x30) /* Interrupt Mask reg */