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Searched refs:ISR (Results 1 – 12 of 12) sorted by relevance

/qemu/hw/char/
H A Dstm32l4x5_usart.c114 REG32(ISR, 0x1C)
120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */
122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */
125 FIELD(ISR, EOBF, 12, 1) /* End of block flag */
126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */
127 FIELD(ISR, CTS, 10, 1) /* CTS flag */
128 FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */
133 FIELD(ISR, IDLE, 4, 1) /* Idle line detected */
134 FIELD(ISR, ORE, 3, 1) /* Overrun error */
136 FIELD(ISR, FE, 1, 1) /* Framing Error */
[all …]
/qemu/hw/net/
H A Dcadence_gem.c160 FIELD(ISR, TX_LOCKUP, 31, 1)
161 FIELD(ISR, RX_LOCKUP, 30, 1)
162 FIELD(ISR, TSU_TIMER, 29, 1)
163 FIELD(ISR, WOL, 28, 1)
164 FIELD(ISR, RECV_LPI, 27, 1)
176 FIELD(ISR, EXT_IRQ, 15, 1)
182 FIELD(ISR, LINK_CHANGE, 9, 1)
183 FIELD(ISR, USXGMII_INT, 8, 1)
185 FIELD(ISR, AMBA_ERROR, 6, 1)
188 FIELD(ISR, TX_USED, 3, 1)
[all …]
/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c38 REG32(ISR, 0x1C)
39 FIELD(ISR, TXE, 7, 1)
40 FIELD(ISR, RXNE, 5, 1)
41 FIELD(ISR, ORE, 3, 1)
/qemu/include/hw/misc/
H A Dxlnx-zynqmp-apu-ctrl.h23 REG32(ISR, 0x10)
24 FIELD(ISR, INV_APB, 0, 1)
/qemu/hw/display/
H A Dtc6393xb.c94 uint8_t ISR; member
184 uint8_t isr = s->scr.ISR; in tc6393xb_sub_irq()
189 s->scr.ISR = isr; in tc6393xb_sub_irq()
215 SCR_REG_B(ISR); in tc6393xb_scr_readb()
272 SCR_REG_B(ISR); in tc6393xb_scr_writeb()
/qemu/hw/net/can/
H A Dtrace-events2 xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
12 xlnx_canfd_update_irq(char *path, uint32_t isr, uint32_t ier, uint32_t irq) "%s: ISR: 0x%08x IER: 0…
/qemu/tests/tcg/multiarch/
H A Dtest-aes-main.c.inc152 verify(&rounds[i].start, &t, "ISB+ISR");
166 verify(&rounds[i - 1].after_sr, &t, "ISB+ISR+AK+IMC");
178 verify(&rounds[i - 1].after_sr, &t, "ISB+ISR+IMC+AK");
/qemu/docs/specs/
H A Dedu.rst75 status register. This needs to be done from the ISR to stop
H A Drocker.txt151 Software should install the Interrupt Service Routine (ISR) before any ports
/qemu/hw/arm/
H A Dpxa2xx.c1275 #define ISR 0x98 /* I2C Status register */ macro
1362 case ISR: in pxa2xx_i2c_read()
1437 case ISR: in pxa2xx_i2c_write()
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c678 REG32(ISR, 0x800)
679 FIELD(ISR, ADDR_DECODE_ERR, 0, 1)
/qemu/qapi/
H A Dvirtio.json140 # @isr: VirtIODevice ISR