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Searched refs:XCHAL_HAVE_CCOUNT (Results 1 – 13 of 13) sorted by relevance

/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h181 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/tests/tcg/xtensa/
H A Dtest_sr.S79 #if XCHAL_HAVE_CCOUNT
H A Dtest_timer.S18 #if XCHAL_HAVE_CCOUNT
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h258 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h185 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h265 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h252 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h233 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h300 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h330 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h351 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h411 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ macro
/qemu/target/xtensa/
H A Doverlay_tool.h138 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \