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Searched refs:aircr (Results 1 – 5 of 5) sorted by relevance

/qemu/hw/intc/
H A Darmv7m_nvic.c188 return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); in exc_targets_secure()
218 (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) { in exc_group_prio()
359 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { in nvic_exec_prio()
373 if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in nvic_exec_prio()
376 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { in nvic_exec_prio()
874 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in armv7m_nvic_complete_irq()
1091 val |= cpu->env.v7m.aircr; in nvic_readl()
1253 !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_readl()
1634 cpu->env.v7m.aircr = value & in nvic_writel()
1762 (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && in nvic_writel()
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/qemu/target/arm/
H A Dmachine.c617 VMSTATE_UINT32(env.v7m.aircr, ARMCPU),
H A Dcpu.c407 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; in arm_cpu_reset_hold()
H A Dcpu.h558 uint32_t aircr; /* only holds r/w state if security extn implemented */ member
/qemu/target/arm/tcg/
H A Dm_helper.c709 exc_secure = !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); in arm_v7m_load_vector()
729 if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in arm_v7m_load_vector()