Searched refs:cfsr (Results 1 – 4 of 4) sorted by relevance
264 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; in v7m_stack_write()267 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; in v7m_stack_write()326 env->v7m.cfsr[secure] |= R_V7M_CFSR_MUNSTKERR_MASK; in v7m_stack_read()338 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK; in v7m_stack_read()383 env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; in HELPER()387 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in HELPER()1283 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in v7m_push_stack()2022 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; in v7m_read_half_insn()2072 env->v7m.cfsr[M_REG_NS] |= in v7m_read_sg_stack_word()2305 env->v7m.cfsr[M_REG_NS] |= in arm_v7m_cpu_do_interrupt()[all …]
405 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),603 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
547 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ member
2307 val = s->cpu->env.v7m.cfsr[attrs.secure]; in nvic_sysreg_read()2312 val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; in nvic_sysreg_read()2441 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; in nvic_sysreg_write()2446 s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); in nvic_sysreg_write()