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/qemu/scripts/
H A Dmeson-buildoptions.sh254 --enable-bpf) printf "%s" -Dbpf=enabled ;;
302 --enable-dmg) printf "%s" -Ddmg=enabled ;;
309 --enable-fdt) printf "%s" -Dfdt=enabled ;;
322 --enable-gio) printf "%s" -Dgio=enabled ;;
328 --enable-gtk) printf "%s" -Dgtk=enabled ;;
340 --enable-hvf) printf "%s" -Dhvf=enabled ;;
353 --enable-kvm) printf "%s" -Dkvm=enabled ;;
387 --enable-lzo) printf "%s" -Dlzo=enabled ;;
413 --enable-oss) printf "%s" -Doss=enabled ;;
415 --enable-pa) printf "%s" -Dpa=enabled ;;
[all …]
H A Dmodinfo-generate.py35 def generate(name, lines, enabled): argument
54 if data.strip() not in enabled:
89 enabled = set()
94 enabled.add(config[0][7:]) # remove CONFIG_
104 moddeps = generate(basename, lines, enabled)
/qemu/hw/core/
H A Dptimer.c91 s->enabled = 0; in ptimer_reload()
120 if (s->enabled == 0) { in ptimer_reload()
128 s->enabled = 0; in ptimer_reload()
169 if (s->enabled == 2) { in ptimer_tick()
171 s->enabled = 0; in ptimer_tick()
301 if (s->enabled) { in ptimer_set_count()
330 if (!s->enabled) in ptimer_stop()
335 s->enabled = 0; in ptimer_stop()
346 if (s->enabled) { in ptimer_set_period()
379 if (s->enabled) { in ptimer_set_period_from_clock()
[all …]
/qemu/hw/intc/
H A Dimx_avic.c43 VMSTATE_UINT64(enabled, IMXAVICState),
63 uint64_t new = s->pending & s->enabled; in imx_avic_update()
127 return s->enabled >> 32; in imx_avic_read()
130 return s->enabled & 0xffffffffULL; in imx_avic_read()
196 return (s->pending & s->enabled & ~s->is_fiq) >> 32; in imx_avic_read()
202 return (s->pending & s->enabled & s->is_fiq) >> 32; in imx_avic_read()
246 s->enabled |= (1ULL << val); in imx_avic_write()
252 s->enabled &= ~(1ULL << val); in imx_avic_write()
256 s->enabled = (s->enabled & 0xffffffffULL) | (val << 32); in imx_avic_write()
260 s->enabled = (s->enabled & 0xffffffff00000000ULL) | val; in imx_avic_write()
[all …]
H A Dgoldfish_pic.c46 s->idx, s->pending, s->enabled); in goldfish_pic_print_info()
51 if (s->pending & s->enabled) { in goldfish_pic_update()
82 value = ctpop32(s->pending & s->enabled); in goldfish_pic_read()
86 value = s->pending & s->enabled; in goldfish_pic_read()
109 s->enabled = 0; in goldfish_pic_write()
113 s->enabled &= ~value; in goldfish_pic_write()
116 s->enabled |= value; in goldfish_pic_write()
143 s->enabled = 0; in goldfish_pic_reset()
166 VMSTATE_UINT32(enabled, GoldfishPICState),
H A Darmv7m_nvic.c264 if (vec->enabled && vec->pending && in nvic_recompute_state_secure()
622 } else if (!vec->enabled) { in do_armv7m_nvic_set_pending()
739 if (!vec->enabled || in armv7m_nvic_set_pending_lazyfp()
785 assert(vec->enabled); in armv7m_nvic_acknowledge_irq()
938 return vec->enabled && in armv7m_nvic_get_ready_status()
2503 VMSTATE_UINT8(enabled, VecInfo),
2593 s->vectors[ARMV7M_EXCP_NMI].enabled = 1; in armv7m_nvic_reset()
2597 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
2598 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; in armv7m_nvic_reset()
2599 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; in armv7m_nvic_reset()
[all …]
/qemu/tests/avocado/
H A Dmem-addr-space-check.py49 self.vm.set_qmp_monitor(enabled=False)
69 self.vm.set_qmp_monitor(enabled=False)
88 self.vm.set_qmp_monitor(enabled=False)
108 self.vm.set_qmp_monitor(enabled=False)
127 self.vm.set_qmp_monitor(enabled=False)
149 self.vm.set_qmp_monitor(enabled=False)
179 self.vm.set_qmp_monitor(enabled=False)
202 self.vm.set_qmp_monitor(enabled=False)
221 self.vm.set_qmp_monitor(enabled=False)
240 self.vm.set_qmp_monitor(enabled=False)
[all …]
/qemu/docs/system/arm/
H A Dcpu-features.rst6 corresponding boolean CPU proprieties that, when enabled, indicate
199 enabled, the feature is supported, and the guest is 64-bit.
222 Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled,
246 1) At least one vector length must be enabled when ``sve`` is enabled.
248 2) If a vector length ``N`` is enabled, then, when KVM is enabled, all
259 no ``sve*`` properties may be enabled.
310 they were not explicitly enabled.
350 then allow them to be auto-enabled::
392 lengths supported by ``max`` defaulting to enabled
421 SVE mode is enabled.
[all …]
/qemu/hw/watchdog/
H A Dwdt_diag288.c28 VMSTATE_BOOL(enabled, DIAG288State),
37 diag288->enabled = false; in wdt_diag288_reset()
71 diag288->enabled = true; in wdt_diag288_handle_timer()
74 if (!diag288->enabled) { in wdt_diag288_handle_timer()
82 if (!diag288->enabled) { in wdt_diag288_handle_timer()
85 diag288->enabled = false; in wdt_diag288_handle_timer()
H A Dwdt_i6300esb.c87 int enabled; /* If true, watchdog is enabled. */ member
116 if (!d->enabled) in OBJECT_DECLARE_SIMPLE_TYPE()
164 d->enabled = 0; in i6300esb_reset()
228 old = d->enabled; in i6300esb_config_write()
229 d->enabled = (data & ESB_WDT_ENABLE) != 0; in i6300esb_config_write()
230 if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */ in i6300esb_config_write()
232 else if (!d->enabled) in i6300esb_config_write()
257 (d->enabled ? ESB_WDT_ENABLE : 0); in i6300esb_config_read()
428 VMSTATE_INT32(enabled, I6300State),
/qemu/hw/input/
H A Dtsc2005.c46 bool enabled; member
205 if (s->enabled != !(data & 0x4000)) { in tsc2005_write()
206 s->enabled = !(data & 0x4000); in tsc2005_write()
208 if (s->busy && !s->enabled) { in tsc2005_write()
211 s->busy = s->busy && s->enabled; in tsc2005_write()
263 s->enabled = false; in tsc2005_pin_update()
286 s->enabled = false; in tsc2005_pin_update()
298 if (!s->enabled || s->busy) { in tsc2005_pin_update()
315 s->enabled = false; in tsc2005_reset()
350 s->enabled = !(value & 1); in tsc2005_txrx_word()
[all …]
/qemu/scripts/tracetool/format/
H A Dh.py39 enabled = 0
41 enabled = 1
46 enabled=enabled)
47 out('#define TRACE_%s_ENABLED %d' % (e.name.upper(), enabled))
/qemu/qapi/
H A Dqmp-registry.c29 cmd->enabled = true; in qmp_register_command()
48 bool enabled, const char *disable_reason) in qmp_toggle_command() argument
54 cmd->enabled = enabled; in qmp_toggle_command()
74 return cmd->enabled; in qmp_command_is_enabled()
/qemu/hw/net/rocker/
H A Drocker_fp.c35 bool enabled; member
59 value->enabled = port->enabled; in fp_port_get_info()
124 if (port->enabled) { in fp_port_eg()
142 if (!port->enabled) { in fp_port_receive_iov()
198 return port->enabled; in fp_port_enabled()
214 port->enabled = true; in fp_port_enable()
220 port->enabled = false; in fp_port_disable()
/qemu/hw/timer/
H A Dsh_timer.c46 int enabled; member
104 if (s->enabled) { in sh_timer_write()
186 if (s->enabled) { in sh_timer_write()
209 trace_sh_timer_start_stop(enable, s->enabled); in sh_timer_start_stop()
211 if (s->enabled && !enable) { in sh_timer_start_stop()
214 if (!s->enabled && enable) { in sh_timer_start_stop()
218 s->enabled = !!enable; in sh_timer_start_stop()
224 s->int_level = s->enabled; in sh_timer_tick()
239 s->enabled = 0; in sh_timer_init()
/qemu/semihosting/
H A Dconfig.c55 bool enabled; member
68 return semihosting.enabled && (!is_user || semihosting.userspace_enabled); in semihosting_enabled()
131 semihosting.enabled = true; in qemu_semihosting_enable()
140 semihosting.enabled = true; in qemu_semihosting_config_options()
143 semihosting.enabled = qemu_opt_get_bool(opts, "enable", in qemu_semihosting_config_options()
/qemu/util/
H A Dqemu-timer.c53 bool enabled; member
131 clock->enabled = (type == QEMU_CLOCK_VIRTUAL ? false : true); in qemu_clock_init()
157 void qemu_clock_enable(QEMUClockType type, bool enabled) in qemu_clock_enable() argument
161 bool old = clock->enabled; in qemu_clock_enable()
162 clock->enabled = enabled; in qemu_clock_enable()
163 if (enabled && !old) { in qemu_clock_enable()
165 } else if (!enabled && old) { in qemu_clock_enable()
221 if (!timer_list->clock->enabled) { in timerlist_deadline_ns()
259 if (!clock->enabled) { in qemu_clock_deadline_ns_all()
514 if (!timer_list->clock->enabled) { in timerlist_run_timers()
/qemu/
H A D.patchew.yml25 enabled: true
42 enabled: true
65 enabled: true
121 enabled: true
128 enabled: false
135 enabled: true
143 enabled: true
150 enabled: false
208 enabled: true
226 enabled: true
[all …]
/qemu/include/io/
H A Dchannel.h130 bool enabled,
148 bool enabled);
150 bool enabled);
512 bool enabled,
528 void qio_channel_set_follow_coroutine_ctx(QIOChannel *ioc, bool enabled);
663 bool enabled);
688 bool enabled);
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c64 bool enabled) in riscv_cpu_write_misa_bit() argument
68 if (enabled) { in riscv_cpu_write_misa_bit()
819 profile->enabled = profile_impl; in riscv_cpu_validate_profile()
825 profile->enabled = profile->enabled && parent_enabled; in riscv_cpu_validate_profile()
943 bool enabled; member
1003 {.misa_bit = _bit, .enabled = _enabled}
1081 profile->enabled = value; in cpu_set_profile()
1088 if (profile->enabled) { in cpu_set_profile()
1123 if (profile->enabled) { in cpu_set_profile()
1140 bool value = profile->enabled; in cpu_get_profile()
[all …]
/qemu/hw/i2c/
H A Di2c_mux_pca954x.c45 bool enabled[PCA9548_CHANNEL_COUNT]; member
86 if (!mux->enabled[i]) { in OBJECT_DECLARE_TYPE()
113 s->enabled[i] = true; in pca954x_enable_channel()
115 s->enabled[i] = false; in pca954x_enable_channel()
209 s->enabled[i] = false; in pca954x_init()
H A Dsmbus_ich9.c83 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled) in ich9_smb_set_irq() argument
87 if (enabled == s->irq_enabled) { in ich9_smb_set_irq()
91 s->irq_enabled = enabled; in ich9_smb_set_irq()
92 pci_set_irq(&s->dev, enabled); in ich9_smb_set_irq()
/qemu/hw/m68k/
H A Dmcf_intc.c30 uint64_t enabled; member
43 active = (s->ipr | s->ifr) & s->enabled & ~s->imr; in mcf_intc_update()
104 s->enabled &= ~(1ull << n); in mcf_intc_write()
106 s->enabled |= (1ull << n); in mcf_intc_write()
161 s->enabled = 0; in mcf_intc_reset()
/qemu/docs/system/i386/
H A Dhyperv.rst22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
23 QEMU, individual enlightenments can be enabled through CPU flags, e.g:
32 When any set of the Hyper-V enlightenments is enabled, QEMU changes hypervisor
80 page (enabled via MSR HV_X64_MSR_REFERENCE_TSC, 0x40000021). Both clocksources
87 When enabled, this enlightenment provides additional communication facilities
144 enabled, it provides HV_X64_MSR_REENLIGHTENMENT_CONTROL (0x40000106),
176 enabled.
230 enabled, it allows L0 (KVM) and L1 (Hyper-V) hypervisors to collaborate to
233 Enlightened VMCS (``hv-evmcs``) feature to also be enabled.
250 enabled, it allows L0 (KVM) to directly handle TLB flush hypercalls from L2
[all …]
/qemu/hw/char/
H A Dnrf51_uart.c46 if (!s->enabled) { in uart_read()
120 if (!s->enabled && (addr != A_UART_ENABLE)) { in uart_write()
167 s->enabled = true; in uart_write()
171 s->enabled = false; in uart_write()
219 s->enabled = false; in nrf51_uart_reset()
302 VMSTATE_BOOL(enabled, NRF51UARTState),

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