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Searched refs:fpccr (Results 1 – 8 of 8) sorted by relevance

/qemu/target/arm/tcg/
H A Dm_helper.c438 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER()
995 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr()
996 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr()
997 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local
1009 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr()
1012 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr()
1016 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr()
1018 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr()
1028 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr()
1049 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER()
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H A Dtranslate-m-nocp.c133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM()
296 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
H A Dtranslate-vfp.c161 tmp = load_cpu_field(v7m.fpccr[M_REG_S]); in gen_update_fp_context()
167 store_cpu_field(tmp, v7m.fpccr[M_REG_S]); in gen_update_fp_context()
/qemu/hw/intc/
H A Darmv7m_nvic.c691 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp()
692 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local
709 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp()
712 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp()
1508 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl()
1516 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl()
1527 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl()
2083 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel()
2109 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel()
2113 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
/qemu/target/arm/
H A Dcpu.c435 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset_hold()
436 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset_hold()
482 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset_hold()
H A Dmachine.c368 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
H A Dcpu.h565 uint32_t fpccr[M_REG_NUM_BANKS]; member
H A Dhelper.c12656 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in cpu_get_tb_cpu_state()
12661 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && in cpu_get_tb_cpu_state()
12673 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in cpu_get_tb_cpu_state()
12674 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { in cpu_get_tb_cpu_state()