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/qemu/docs/specs/
H A Dppc-spapr-hcalls.rst2 sPAPR hypervisor calls
6 a set of hypervisor calls (a.k.a. hcalls) defined in the Linux on Power
9 which is what PowerVM, the IBM proprietary hypervisor, adheres to.
13 In addition to those calls, we have added our own private hypervisor
31 calls our private H_RTAS hypervisor call to pass the RTAS calls to QEMU.
53 PAPR and LoPAR provides a set of hypervisor calls to perform cacheable or
H A Dvmw_pvscsi-spec.rst14 The interface is based on a memory area shared between hypervisor and VM.
18 The registers area is used to raise hypervisor interrupts and issue device
20 commands from VM to hypervisor and to transfer messages produced by
21 hypervisor to VM. Data itself is transferred via virtual scatter-gather DMA.
H A Dsev-guest-firmware.rst97 A hypervisor reads the CS segment base and IP value. The CS segment
99 the hypervisor must left shift the value of the CS segment base by 16
109 This describes the guest RAM area where the hypervisor should inject the
118 This describes the guest RAM area where the hypervisor should install a
H A Dvirt-ctlr.rst6 guest kernel to send command to the host hypervisor.
20 This register allows the kernel to send the commands to the hypervisor.
H A Dppc-spapr-xive.rst8 directly to virtual processors without hypervisor assistance.
15 the hypervisor provides identical interfaces and similar
22 the hypervisor provides new interfaces to manage the XIVE control
65 VMs running under a L1 hypervisor (KVM on pSeries). In that case, the
66 hypervisor will not advertise the KVM capability and QEMU will use the
190 contains a list of priorities that the hypervisor has reserved for
227 In the case of a ``pseries`` machine, QEMU acts as the hypervisor and only
H A Dppc-spapr-uv-hcalls.rst24 the hypervisor to orchestrate the movement of guest memory to secure memory and
40 session key. Though the hypervisor will see the in and out buffers in raw form,
H A Dppc-xive.rst11 deliver interrupts directly to virtual processors without hypervisor
127 - hypervisor exception
151 is for the hypervisor, ring 1 view. The third (page address ending in
H A Dvmgenid.rst50 - **R6** The hypervisor shall expose a _HID (hardware identifier) object
51 in the VMGenId device's scope that is unique to the hypervisor vendor.
H A Dppc-spapr-hotplug.rst8 host-bridges, which are generally managed by the host/hypervisor and provided
72 convention used to assign them to pSeries guests on pHyp (the hypervisor
315 For most DR operations, the hypervisor will issue host->guest add/remove events
/qemu/docs/system/ppc/
H A Dpseries.rst11 capable of acting as a hypervisor OS, providing, on that role, nested
23 PowerVM hypervisor with VIOS managing LPARs.
107 running the IBM PowerVM hypervisor with LPARs.
110 hypervisor and non-Linux guests in mind, you should use the virtio counterparts
171 on hypervisor mode on a Power processor (this function was restricted to
172 PowerVM, the IBM proprietary hypervisor).
193 KVM-HV uses the hypervisor mode of more recent Power processors, that allow
200 hypervisor mode of the Power CPU, it wasn't possible to run KVM-HV on a guest.
266 pool of secure memory which cannot be accessed by the hypervisor.
270 memory, where it cannot be eavesdropped by a compromised hypervisor.
/qemu/docs/devel/
H A Dnested-papr.txt25 hypervisor and run nested guests through the use of hypercalls, if the
26 hypervisor has implemented them. The terms L0, L1, and L2 are used to
27 refer to different software entities. L0 is the hypervisor mode entity
28 that would normally be called the "host" or "hypervisor". L1 is a
31 and controlled by L1 acting as a hypervisor. A significant design change
/qemu/docs/system/i386/
H A Dhyperv.rst16 compatible hypervisor and use Hyper-V specific features.
32 When any set of the Hyper-V enlightenments is enabled, QEMU changes hypervisor
42 hypervisor. It is known that some Windows versions will do this even when they
43 see 'hypervisor' CPU flag.
53 hypervisor. A special value 0xffffffff indicates "never notify".
113 implements TLB shoot-down through hypervisor enabling the optimization.
120 through APIC requires more than one access (and thus exit to the hypervisor).
148 the hypervisor) until it is ready to switch to the new one. This, in conjunction
163 hypervisors making L2 exits to the hypervisor faster. The feature is Intel-only.
251 guest without the need to exit to L1 (Hyper-V) hypervisor. While the feature is
H A Damd-memory-encryption.rst23 hypervisor to perform functions on behalf of a guest, there is architectural
26 the hypervisor to satisfy the requested function.
46 The guest policy is passed as plaintext. A hypervisor may choose to read it,
111 guest register state is encrypted and cannot be updated by the VMM/hypervisor,
118 - Requires in-kernel irqchip - the burden is placed on the hypervisor to
233 Since the memory contents of a SEV guest are encrypted, hypervisor access to
235 then a hypervisor can use the DEBUG_DECRYPT and DEBUG_ENCRYPT commands to access
/qemu/docs/system/
H A Dconfidential-guest-support.rst5 guest's memory and other state, meaning that a compromised hypervisor
8 protection from a compromised hypervisor. This is obviously
H A Dguest-loader.rst8 aimed at a particular use case of loading hypervisor guests. This is
27 In the above example the Xen hypervisor is loaded by the -kernel
/qemu/docs/system/s390x/
H A Dprotvirt.rst5 (PVMs) are encrypted or inaccessible to the hypervisor, effectively
19 Running PVMs requires using the KVM hypervisor.
/qemu/docs/about/
H A Dindex.rst11 hypervisor such as KVM, Xen or Hypervisor.Framework to allow the
/qemu/qapi/
H A Drun-state.json500 # @type: Crash type that defines the hypervisor specific information
619 # @hypervisor: memory failure at QEMU process address space. (none
627 'data': [ 'hypervisor',
643 # action-required failures if the recipient is the hypervisor;
/qemu/target/sparc/
H A Dtranslate.c187 bool hypervisor; member
300 #define hypervisor(dc) 0 macro
303 #define hypervisor(dc) (dc->hypervisor) macro
304 #define supervisor(dc) (dc->supervisor | dc->hypervisor)
307 #define hypervisor(dc) 0 macro
1596 if (hypervisor(dc)) { in resolve_asi()
3014 TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd,
3580 TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp) in TRANS()
3587 TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba) in TRANS()
3601 TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc), in TRANS()
[all …]
/qemu/
H A DREADME.rst12 hypervisor to manage the CPU. With hypervisor support, QEMU can achieve
/qemu/docs/system/riscv/
H A Dvirt.rst26 The hypervisor extension has been enabled for the default CPU, so virtual
27 machines with hypervisor extension can simply be used without explicitly
/qemu/docs/interop/
H A Dqemu-ga.rst13 machines. It allows the hypervisor host to perform various operations
/qemu/pc-bios/optionrom/
H A Dkvmvapic.S28 # announce presence to the hypervisor
/qemu/pc-bios/
H A DREADME43 run an hypervisor OS or simply a host OS on the "baremetal"
/qemu/target/ppc/translate/
H A Dstorage-ctrl-impl.c.inc204 * making it hypervisor privileged.

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