/qemu/pc-bios/ |
H A D | canyonlands.dts | 54 interrupt-controller; 59 #interrupt-cells = <2>; 64 interrupt-controller; 69 #interrupt-cells = <2>; 76 interrupt-controller; 81 #interrupt-cells = <2>; 88 interrupt-controller; 93 #interrupt-cells = <2>; 184 #interrupt-cells = <1>; 499 interrupt-map = < [all …]
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H A D | bamboo.dts | 50 UIC0: interrupt-controller0 { 52 interrupt-controller; 57 #interrupt-cells = <0x2>; 96 /* interrupt-parent = <&UIC1>; */ 107 /* interrupt-parent = <&UIC1>; */ 117 interrupt-parent = <&UIC0>; 128 interrupt-parent = <&UIC0>; 136 interrupt-parent = <&UIC0>; 144 interrupt-parent = <&UIC0>; 158 #interrupt-cells = <1>; [all …]
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H A D | petalogix-s3adsp1800.dts | 79 xlnx,interrupt-is-edge = <0x00>; 104 xlnx,use-interrupt = <0x01>; 120 interrupt-parent = <0x01>; 213 interrupt-parent = <0x01>; 222 xlnx,interrupt-present = <0x01>; 235 interrupt-parent = <0x01>; 258 interrupt-controller@81800000 { 259 #interrupt-cells = <0x02>; 261 interrupt-controller; 270 interrupt-parent = <0x01>;
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H A D | petalogix-ml605.dts | 98 xlnx,interrupt-is-edge = < 0x00 >; 126 xlnx,use-interrupt = < 0x01 >; 144 interrupt-parent = < &intc >; 182 interrupt-parent = < &intc >; 205 interrupt-parent = < &intc >; 222 interrupt-parent = < &intc >; 234 intc: interrupt-controller@81800000 { 235 #interrupt-cells = < 0x02 >; 237 interrupt-controller;
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/qemu/tests/tcg/xtensa/ |
H A D | test_timer.S | 66 rsr a2, interrupt 77 rsr a3, interrupt 83 rsr a2, interrupt 91 rsr a2, interrupt 104 rsr a3, interrupt 106 rsr a5, interrupt 119 rsr a2, interrupt 133 rsr a2, interrupt 156 rsr a2, interrupt 168 rsr a2, interrupt [all …]
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H A D | test_interrupt.S | 41 test_suite interrupt 58 rsr a2, interrupt 62 rsr a2, interrupt 99 rsr a3, interrupt 105 rsr a3, interrupt 121 rsr a3, interrupt 140 rsr a3, interrupt 159 rsr a3, interrupt 178 rsr a3, interrupt
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/qemu/docs/specs/ |
H A D | edu.rst | 63 raise interrupt after finishing factorial computation 65 0x24 (RO) : interrupt status register 66 It contains values which raised the interrupt (see interrupt raise 69 0x60 (WO) : interrupt raise register 70 Raise an interrupt. The value will be put to the interrupt status 73 0x64 (WO) : interrupt acknowledge register 74 Clear an interrupt. The value will be cleared from the interrupt 95 raise interrupt 0x100 after finishing the DMA 101 appears in interrupt status register when the interrupt is raised and has to 102 be written to the interrupt acknowledge register to lower it. [all …]
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H A D | ppc-spapr-xive.rst | 4 The POWER9 processor comes with a new interrupt controller 6 Engine". It supports a larger number of interrupt sources and offers 11 processors can run under two interrupt modes: 23 structures, and provides direct control for interrupt management 26 Which interrupt modes can be used by the machine is negotiated with 30 Both interrupt mode share the same IRQ number space. See below for the 36 QEMU advertises the supported interrupt modes in the device tree 41 The interrupt modes supported by the machine depend on the CPU type 49 The chosen interrupt mode is activated after a reconfiguration done 104 (3) QEMU fails at CAS with ``Guest requested unavailable interrupt [all …]
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H A D | vmw_pvscsi-spec.rst | 30 issue device interrupts, and control interrupt masking. 53 The following interrupt types are supported by the PVSCSI device: 66 register. If a bit is set it means the interrupt is enabled, and if 67 it is clear then the interrupt is disabled. 69 The interrupt modes supported are legacy, MSI and MSI-X. 71 register is used to check which interrupt has arrived. Interrupts are 72 acknowledged when the corresponding bit is written to the interrupt 82 b. Windows driver reads interrupt status register here 114 a. Upon completion interrupt arrival process completion
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H A D | ppc-xive.rst | 2 POWER9 XIVE interrupt controller 5 The POWER9 processor comes with a new interrupt controller 10 XIVE are to support a larger number of interrupt sources and to 29 Controller (VC). It handles event coalescing and perform interrupt 33 Controller (PC). It maintains the interrupt context state of each 34 thread and handles the delivery of the external interrupt to the 69 tctx: Thread interrupt Context registers 121 XIVE thread interrupt context 134 lets the thread handle priority management and interrupt 173 The O/S handles the interrupt and when done, performs an EOI using a [all …]
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H A D | ivshmem-spec.rst | 14 In the latter case, the device can additionally interrupt its peers, and 41 - If you additionally need the capability for peers to interrupt each 65 bit 0: peer interrupt (rev 0) 69 bit 0: peer interrupt (rev 0) 83 together control the legacy INTx interrupt when the device has no 101 and its low 16 bits select an interrupt vector. 105 If the interrupt hasn't completed setup, the write is ignored. The 112 interrupt vectors are connected. 121 communicate the interrupt vector to guest software then. 124 different events have occurred. The semantics of interrupt vectors [all …]
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H A D | acpi_hw_reduced_hotplug.rst | 15 single interrupt for the GED device, relying on an IO memory region 16 to communicate the type of device affected by the interrupt. This way, 17 we can support up to 32 events with a unique interrupt.
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/qemu/hw/vfio/ |
H A D | platform.c | 76 intp->interrupt = g_new0(EventNotifier, 1); in vfio_init_intp() 77 ret = event_notifier_init(intp->interrupt, 0); in vfio_init_intp() 79 g_free(intp->interrupt); in vfio_init_intp() 90 g_free(intp->interrupt); in vfio_init_intp() 116 int32_t fd = event_notifier_get_fd(intp->interrupt); in vfio_set_trigger_eventfd() 196 event_notifier_get_fd(intp->interrupt)); in vfio_intp_inject_pending_lockheld() 238 event_notifier_test_and_clear(intp->interrupt); in vfio_intp_interrupt() 243 event_notifier_get_fd(intp->interrupt)); in vfio_intp_interrupt() 245 ret = event_notifier_test_and_clear(intp->interrupt); in vfio_intp_interrupt() 248 event_notifier_get_fd(intp->interrupt), ret); in vfio_intp_interrupt() [all …]
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H A D | pci.c | 245 if (vdev->interrupt != VFIO_INT_INTx) { in vfio_intx_routing_notifier() 311 vdev->interrupt = VFIO_INT_INTx; in vfio_intx_enable() 332 vdev->interrupt = VFIO_INT_NONE; in vfio_intx_disable() 353 if (vdev->interrupt == VFIO_INT_MSIX) { in vfio_msi_interrupt() 363 } else if (vdev->interrupt == VFIO_INT_MSI) { in vfio_msi_interrupt() 676 vdev->interrupt = VFIO_INT_MSIX; in vfio_msix_enable() 761 vdev->interrupt = VFIO_INT_MSI; in vfio_msi_enable() 811 vdev->interrupt = VFIO_INT_NONE; in vfio_msi_disable_common() 1329 if (vdev->interrupt == VFIO_INT_MSIX) { in vfio_disable_interrupts() 1335 if (vdev->interrupt == VFIO_INT_INTx) { in vfio_disable_interrupts() [all …]
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H A D | pci.h | 77 EventNotifier interrupt; /* eventfd triggered on interrupt */ member 94 EventNotifier interrupt; member 136 int interrupt; /* Current interrupt type */ member
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/qemu/tests/tcg/multiarch/system/ |
H A D | Makefile.softmmu-target | 29 run-gdbstub-interrupt: interrupt 36 --bin $< --test $(MULTIARCH_SRC)/gdbstub/interrupt.py, \ 66 MULTIARCH_RUNS += run-gdbstub-memory run-gdbstub-interrupt \
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/qemu/hw/input/ |
H A D | ads7846.c | 23 qemu_irq interrupt; member 62 if (s->interrupt) in OBJECT_DECLARE_SIMPLE_TYPE() 63 qemu_set_irq(s->interrupt, s->pressure == 0); in OBJECT_DECLARE_SIMPLE_TYPE() 148 qdev_init_gpio_out(dev, &s->interrupt, 1); in ads7846_realize()
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/qemu/hw/dma/ |
H A D | trace-events | 26 pl330_fault_abort(void) "abort interrupt raised" 30 pl330_dmakill(void) "abort interrupt lowered" 34 pl330_dmasev_evirq(uint8_t ev_id) "event interrupt raised %"PRId8 45 pl330_iomem_write_clr(int i) "event interrupt lowered %d"
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/qemu/tests/qtest/ |
H A D | bcm2835-i2c-test.c | 42 int interrupt = read ? BCM2835_I2C_C_INTR : BCM2835_I2C_C_INTT; in bcm2835_i2c_init_transfer() local 46 BCM2835_I2C_C_ST | BCM2835_I2C_C_CLEAR | interrupt | read); in bcm2835_i2c_init_transfer()
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/qemu/hw/s390x/ |
H A D | trace-events | 9 …chid, uint32_t intparm, uint8_t isc, const char *conditional) "CSS: I/O interrupt on sch %x.%x.%04… 10 css_adapter_interrupt(uint8_t isc) "CSS: adapter I/O interrupt (isc 0x%x)" 31 s390_pci_kvm_aif(const char *str) "Failed to %s interrupt forwarding"
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/qemu/docs/devel/ |
H A D | multi-process.rst | 137 vhost interrupt acceleration 144 that triggers the device interrupt in the guest when the eventfd is 381 interrupt receipt 509 interrupt injection 515 depend on the type of interrupt being raised. 524 ``pci_bus_irqs()``) to send a interrupt request back to the QEMU 831 interrupt acceleration 839 interrupt. 849 device has not de-asserted its interrupt. 857 The interrupt route can be found with [all …]
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/qemu/target/ppc/ |
H A D | excp_helper.c | 2166 switch (interrupt) { in p7_deliver_interrupt() 2209 interrupt); in p7_deliver_interrupt() 2217 switch (interrupt) { in p8_deliver_interrupt() 2280 interrupt); in p8_deliver_interrupt() 2298 switch (interrupt) { in p9_deliver_interrupt() 2360 interrupt); in p9_deliver_interrupt() 2382 switch (interrupt) { in ppc_deliver_interrupt() 2478 interrupt); in ppc_deliver_interrupt() 2513 int interrupt; in ppc_cpu_exec_interrupt() local 2520 if (interrupt == 0) { in ppc_cpu_exec_interrupt() [all …]
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/qemu/target/i386/whpx/ |
H A D | whpx-apic.c | 196 WHV_INTERRUPT_CONTROL interrupt = { in whpx_send_msi() local 210 &interrupt, sizeof(interrupt)); in whpx_send_msi()
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/qemu/docs/system/riscv/ |
H A D | virt.rst | 35 information about the addresses, interrupt lines and other configuration of 105 This option allows selecting interrupt controller defined by the AIA 106 (advanced interrupt architecture) specification. The "aia=aplic" selects 107 APLIC (advanced platform level interrupt controller) to handle wired 109 message signaled interrupt controller) to handle both wired interrupts and
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/qemu/hw/timer/ |
H A D | aspeed_timer.c | 187 bool interrupt = false; in aspeed_timer_expire() local 197 interrupt = timer_overflow_interrupt(t) || !t->match[0] || !t->match[1]; in aspeed_timer_expire() 199 interrupt = true; in aspeed_timer_expire() 201 interrupt = true; in aspeed_timer_expire() 204 if (interrupt) { in aspeed_timer_expire()
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