/qemu/target/arm/tcg/ |
H A D | cpu-v7m.c | 62 cpu->isar.id_pfr0 = 0x00000030; in cortex_m0_initfn() 63 cpu->isar.id_pfr1 = 0x00000200; in cortex_m0_initfn() 64 cpu->isar.id_dfr0 = 0x00100000; in cortex_m0_initfn() 114 cpu->isar.mvfr0 = 0x10110021; in cortex_m4_initfn() 115 cpu->isar.mvfr1 = 0x11000011; in cortex_m4_initfn() 116 cpu->isar.mvfr2 = 0x00000000; in cortex_m4_initfn() 144 cpu->isar.mvfr0 = 0x10110221; in cortex_m7_initfn() 145 cpu->isar.mvfr1 = 0x12000011; in cortex_m7_initfn() 146 cpu->isar.mvfr2 = 0x00000040; in cortex_m7_initfn() 176 cpu->isar.mvfr0 = 0x10110021; in cortex_m33_initfn() [all …]
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H A D | cpu64.c | 92 cpu->isar.id_aa64pfr1 = 0; in aarch64_a35_initfn() 94 cpu->isar.id_aa64dfr1 = 0; in aarch64_a35_initfn() 96 cpu->isar.id_aa64isar1 = 0; in aarch64_a35_initfn() 98 cpu->isar.id_aa64mmfr1 = 0; in aarch64_a35_initfn() 124 cpu->isar.dbgdevid1 = 0x2; in aarch64_a35_initfn() 131 cpu->isar.mvfr0 = 0x10110222; in aarch64_a35_initfn() 132 cpu->isar.mvfr1 = 0x12111111; in aarch64_a35_initfn() 133 cpu->isar.mvfr2 = 0x00000043; in aarch64_a35_initfn() 185 t = cpu->isar.id_aa64pfr0; in cpu_arm_set_rme() 187 cpu->isar.id_aa64pfr0 = t; in cpu_arm_set_rme() [all …]
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H A D | cpu32.c | 28 t = cpu->isar.id_isar5; in aa32_max_features() 47 t = cpu->isar.mvfr1; in aa32_max_features() 50 cpu->isar.mvfr1 = t; in aa32_max_features() 52 t = cpu->isar.mvfr2; in aa32_max_features() 55 cpu->isar.mvfr2 = t; in aa32_max_features() 120 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm926_initfn() 121 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); in arm926_initfn() 122 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); in arm926_initfn() 162 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm1026_initfn() 163 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); in arm1026_initfn() [all …]
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H A D | translate.h | 26 const ARMISARegisters *isar; member 481 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
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H A D | helper-a64.c | 768 &env_archcpu(env)->isar); in cpsr_write_from_spsr_elx() 853 spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); in HELPER()
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H A D | op_helper.c | 489 mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); in HELPER()
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H A D | translate.c | 2635 mask &= aarch32_cpsr_valid_mask(s->features, s->isar); in msr_mask() 9106 dc->isar = &cpu->isar; in arm_tr_init_disas_context()
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H A D | translate-a64.c | 14099 dc->isar = &arm_cpu->isar; in aarch64_tr_init_disas_context()
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/qemu/target/arm/ |
H A D | cpu64.c | 293 t = cpu->isar.id_aa64pfr0; in cpu_arm_set_sve() 295 cpu->isar.id_aa64pfr0 = t; in cpu_arm_set_sve() 348 t = cpu->isar.id_aa64pfr1; in cpu_arm_set_sme() 350 cpu->isar.id_aa64pfr1 = t; in cpu_arm_set_sme() 365 t = cpu->isar.id_aa64smfr0; in cpu_arm_set_sme_fa64() 367 cpu->isar.id_aa64smfr0 = t; in cpu_arm_set_sme_fa64() 586 t = cpu->isar.id_aa64mmfr0; in arm_cpu_lpa2_finalize() 631 cpu->isar.id_isar6 = 0; in aarch64_a57_initfn() 638 cpu->isar.dbgdevid1 = 0x2; in aarch64_a57_initfn() 689 cpu->isar.id_isar6 = 0; in aarch64_a53_initfn() [all …]
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H A D | cpu.c | 2302 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); in arm_cpu_realizefn() 2303 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); in arm_cpu_realizefn() 2304 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, in arm_cpu_realizefn() 2308 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, in arm_cpu_realizefn() 2334 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); in arm_cpu_realizefn() 2344 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, in arm_cpu_realizefn() 2346 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, in arm_cpu_realizefn() 2388 cpu->isar.id_dfr0 = in arm_cpu_realizefn() 2393 cpu->isar.id_dfr0 = in arm_cpu_realizefn() 2396 cpu->isar.id_dfr0 = in arm_cpu_realizefn() [all …]
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H A D | kvm.c | 56 ARMISARegisters isar; member 292 err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, in kvm_arm_get_host_cpu_features() 344 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, in kvm_arm_get_host_cpu_features() 346 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, in kvm_arm_get_host_cpu_features() 348 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, in kvm_arm_get_host_cpu_features() 375 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, in kvm_arm_get_host_cpu_features() 377 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, in kvm_arm_get_host_cpu_features() 379 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, in kvm_arm_get_host_cpu_features() 381 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, in kvm_arm_get_host_cpu_features() 415 ahcf->isar.dbgdidr = dbgdidr; in kvm_arm_get_host_cpu_features() [all …]
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H A D | internals.h | 1001 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; in arm_num_brps() 1003 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; in arm_num_brps() 1015 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; in arm_num_wrps() 1017 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; in arm_num_wrps() 1029 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; in arm_num_ctx_cmps() 1031 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; in arm_num_ctx_cmps() 1626 return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; in pmu_num_counters()
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H A D | debug_helper.c | 1172 if (cpu->isar.dbgdidr != 0) { in define_debug_regs() 1177 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, in define_debug_regs() 1192 if (extract32(cpu->isar.dbgdidr, 15, 1)) { in define_debug_regs() 1197 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid, in define_debug_regs() 1207 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid1, in define_debug_regs()
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H A D | gdbstub.c | 488 if (isar_feature_aa64_sve(&cpu->isar)) { in arm_cpu_register_gdb_regs_for_features() 504 if (isar_feature_aa64_pauth(&cpu->isar)) { in arm_cpu_register_gdb_regs_for_features()
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H A D | helper.c | 7596 .resetvalue = cpu->isar.reset_pmcr_el0, in define_pmu_regs() 7680 uint64_t pfr1 = cpu->isar.id_pfr1; in id_pfr1_read() 7691 uint64_t pfr0 = cpu->isar.id_aa64pfr0; in id_aa64pfr0_read() 8726 .resetvalue = cpu->isar.id_pfr0 }, in register_cp_regs_for_features() 8737 .resetvalue = cpu->isar.id_pfr1, in register_cp_regs_for_features() 8749 .resetvalue = cpu->isar.id_dfr0 }, in register_cp_regs_for_features() 9036 .resetvalue = cpu->isar.mvfr0 }, in register_cp_regs_for_features() 9041 .resetvalue = cpu->isar.mvfr1 }, in register_cp_regs_for_features() 9046 .resetvalue = cpu->isar.mvfr2 }, in register_cp_regs_for_features() 9083 .resetvalue = cpu->isar.id_pfr2 }, in register_cp_regs_for_features() [all …]
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H A D | ptw.c | 107 FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); in arm_pamax() 315 if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { in granule_protection_check() 1730 ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); in get_phys_addr_lpae()
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H A D | cpu-features.h | 1024 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
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H A D | cpu.h | 1024 } isar; member
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/qemu/hw/intc/ |
H A D | armv7m_nvic.c | 1266 return cpu->isar.id_pfr0; in nvic_readl() 1271 return cpu->isar.id_pfr1; in nvic_readl() 1276 return cpu->isar.id_dfr0; in nvic_readl() 1286 return cpu->isar.id_mmfr0; in nvic_readl() 1291 return cpu->isar.id_mmfr1; in nvic_readl() 1296 return cpu->isar.id_mmfr2; in nvic_readl() 1301 return cpu->isar.id_mmfr3; in nvic_readl() 1306 return cpu->isar.id_isar0; in nvic_readl() 1541 return cpu->isar.mvfr0; in nvic_readl() 1543 return cpu->isar.mvfr1; in nvic_readl() [all …]
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/qemu/target/arm/hvf/ |
H A D | hvf.c | 308 ARMISARegisters isar; member 885 ahcf->isar = host_isar; in hvf_arm_get_host_cpu_features() 922 cpu->isar = arm_host_cpu_features.isar; in hvf_arm_set_cpu_features_from_host() 995 &arm_cpu->isar.id_aa64mmfr0); in hvf_arch_init_vcpu()
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