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Searched refs:memmap (Results 1 – 25 of 29) sorted by relevance

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/qemu/hw/riscv/
H A Dopentitan.c255 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); in lowrisc_ibex_soc_realize()
259 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); in lowrisc_ibex_soc_realize()
269 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); in lowrisc_ibex_soc_realize()
271 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); in lowrisc_ibex_soc_realize()
283 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); in lowrisc_ibex_soc_realize()
285 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); in lowrisc_ibex_soc_realize()
287 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); in lowrisc_ibex_soc_realize()
291 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); in lowrisc_ibex_soc_realize()
295 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); in lowrisc_ibex_soc_realize()
297 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); in lowrisc_ibex_soc_realize()
[all …]
H A Dmicrochip_pfsoc.c260 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); in microchip_pfsoc_soc_realize()
291 memmap[MICROCHIP_PFSOC_PLIC].size); in microchip_pfsoc_soc_realize()
314 memmap[MICROCHIP_PFSOC_AXISW].base, in microchip_pfsoc_soc_realize()
385 memmap[MICROCHIP_PFSOC_SPI0].base, in microchip_pfsoc_soc_realize()
388 memmap[MICROCHIP_PFSOC_SPI1].base, in microchip_pfsoc_soc_realize()
393 memmap[MICROCHIP_PFSOC_I2C0].base, in microchip_pfsoc_soc_realize()
396 memmap[MICROCHIP_PFSOC_I2C1].base, in microchip_pfsoc_soc_realize()
401 memmap[MICROCHIP_PFSOC_CAN0].base, in microchip_pfsoc_soc_realize()
404 memmap[MICROCHIP_PFSOC_CAN1].base, in microchip_pfsoc_soc_realize()
409 memmap[MICROCHIP_PFSOC_USB].base, in microchip_pfsoc_soc_realize()
[all …]
H A Dsifive_e.c77 const MemMapEntry *memmap = sifive_e_memmap; in sifive_e_machine_init() local
96 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()
196 const MemMapEntry *memmap = sifive_e_memmap; in sifive_e_soc_realize() local
208 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); in sifive_e_soc_realize()
221 memmap[SIFIVE_E_DEV_PLIC].size); in sifive_e_soc_realize()
265 memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); in sifive_e_soc_realize()
267 memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); in sifive_e_soc_realize()
271 memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); in sifive_e_soc_realize()
273 memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); in sifive_e_soc_realize()
275 memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); in sifive_e_soc_realize()
[all …]
H A Dsifive_u.c159 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, in create_fdt()
228 0x0, memmap[SIFIVE_U_DEV_OTP].base, in create_fdt()
229 0x0, memmap[SIFIVE_U_DEV_OTP].size); in create_fdt()
243 0x0, memmap[SIFIVE_U_DEV_PRCI].base, in create_fdt()
277 0x0, memmap[SIFIVE_U_DEV_PLIC].base, in create_fdt()
408 0x0, memmap[SIFIVE_U_DEV_GEM].base, in create_fdt()
409 0x0, memmap[SIFIVE_U_DEV_GEM].size, in create_fdt()
840 memmap[SIFIVE_U_DEV_PLIC].size); in sifive_u_soc_realize()
919 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); in sifive_u_soc_realize()
922 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); in sifive_u_soc_realize()
[all …]
H A Dvirt.c330 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); in create_fdt_socket_clint()
371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); in create_fdt_socket_aclint()
442 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); in create_fdt_socket_plic()
813 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, in create_fdt_virtio()
852 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); in create_fdt_pcie()
855 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, in create_fdt_pcie()
858 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, in create_fdt_pcie()
885 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); in create_fdt_reset()
941 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); in create_fdt_rtc()
1168 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, in virt_create_plic()
[all …]
H A Dspike.c51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, in create_fdt() argument
83 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); in create_fdt()
158 clint_addr = memmap[SPIKE_CLINT].base + in create_fdt()
159 (memmap[SPIKE_CLINT].size * socket); in create_fdt()
165 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); in create_fdt()
196 const MemMapEntry *memmap = spike_memmap; in spike_board_init() local
200 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; in spike_board_init()
249 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, in spike_board_init()
252 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + in spike_board_init()
265 memmap[SPIKE_MROM].size, &error_fatal); in spike_board_init()
[all …]
H A Dvirt-acpi-build.c79 imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + in riscv_acpi_madt_add_rintc()
191 .base_addr.addr = s->memmap[VIRT_UART0].base, in spcr_setup()
393 const MemMapEntry *memmap = s->memmap; in build_dsdt() local
410 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); in build_dsdt()
418 memmap[VIRT_VIRTIO].size, in build_dsdt()
423 memmap[VIRT_VIRTIO].size, in build_dsdt()
429 memmap[VIRT_VIRTIO].size, in build_dsdt()
542 aplic_addr = s->memmap[VIRT_PLIC].base + in build_madt()
603 mem_base = vms->memmap[VIRT_DRAM].base; in build_srat()
650 .base = s->memmap[VIRT_PCIE_ECAM].base, in virt_acpi_build()
[all …]
/qemu/hw/tricore/
H A Dtc27x_soc.c106 sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size); in tc27x_soc_init_memory_mapping()
108 sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size); in tc27x_soc_init_memory_mapping()
110 sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size); in tc27x_soc_init_memory_mapping()
112 sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size); in tc27x_soc_init_memory_mapping()
114 sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size); in tc27x_soc_init_memory_mapping()
116 sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size); in tc27x_soc_init_memory_mapping()
122 sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size); in tc27x_soc_init_memory_mapping()
126 sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size); in tc27x_soc_init_memory_mapping()
131 sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size); in tc27x_soc_init_memory_mapping()
135 sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size); in tc27x_soc_init_memory_mapping()
[all …]
/qemu/hw/arm/
H A Dallwinner-h3.c191 rom_size, s->memmap[AW_H3_DEV_SRAM_A1], in allwinner_h3_bootrom_setup()
199 s->memmap = allwinner_h3_memmap; in allwinner_h3_init()
383 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0], in allwinner_h3_realize()
386 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1], in allwinner_h3_realize()
389 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2], in allwinner_h3_realize()
392 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3], in allwinner_h3_realize()
396 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0], in allwinner_h3_realize()
399 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1], in allwinner_h3_realize()
402 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2], in allwinner_h3_realize()
405 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3], in allwinner_h3_realize()
[all …]
H A Daspeed_ast10x0.c205 sc->memmap[ASPEED_DEV_IOMEM], in aspeed_soc_ast1030_realize()
229 sc->memmap[ASPEED_DEV_SRAM], in aspeed_soc_ast1030_realize()
278 sc->memmap[ASPEED_DEV_PECI]); in aspeed_soc_ast1030_realize()
323 sc->memmap[ASPEED_DEV_TIMER1]); in aspeed_soc_ast1030_realize()
357 sc->memmap[ASPEED_DEV_SPI1 + i]); in aspeed_soc_ast1030_realize()
375 sc->memmap[ASPEED_DEV_HACE]); in aspeed_soc_ast1030_realize()
397 sc->memmap[ASPEED_DEV_GPIO]); in aspeed_soc_ast1030_realize()
402 sc->memmap[ASPEED_DEV_PWM], 0x100); in aspeed_soc_ast1030_realize()
405 sc->memmap[ASPEED_DEV_ESPI], 0x800); in aspeed_soc_ast1030_realize()
408 sc->memmap[ASPEED_DEV_UDC], 0x1000); in aspeed_soc_ast1030_realize()
[all …]
H A Daspeed_ast2400.c318 sc->memmap[ASPEED_DEV_TIMER1]); in aspeed_ast2400_soc_realize()
352 sc->memmap[ASPEED_DEV_PECI]); in aspeed_ast2400_soc_realize()
380 sc->memmap[ASPEED_DEV_SPI1 + i]); in aspeed_ast2400_soc_realize()
401 sc->memmap[ASPEED_DEV_SDMC]); in aspeed_ast2400_soc_realize()
429 sc->memmap[ASPEED_DEV_ETH1 + i]); in aspeed_ast2400_soc_realize()
439 sc->memmap[ASPEED_DEV_XDMA]); in aspeed_ast2400_soc_realize()
448 sc->memmap[ASPEED_DEV_GPIO]); in aspeed_ast2400_soc_realize()
457 sc->memmap[ASPEED_DEV_SDHCI]); in aspeed_ast2400_soc_realize()
499 sc->memmap[ASPEED_DEV_HACE]); in aspeed_ast2400_soc_realize()
528 sc->memmap = aspeed_soc_ast2400_memmap; in aspeed_soc_ast2400_class_init()
[all …]
H A Dallwinner-r40.c258 rom_size, s->memmap[AW_R40_DEV_SRAM_A1], in allwinner_r40_bootrom_setup()
270 s->memmap = allwinner_r40_memmap; in allwinner_r40_init()
421 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1); in allwinner_r40_realize()
423 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2); in allwinner_r40_realize()
425 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3); in allwinner_r40_realize()
431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); in allwinner_r40_realize()
471 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i]; in allwinner_r40_realize()
492 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i]; in allwinner_r40_realize()
508 s->memmap[AW_R40_DEV_DRAMCOM]); in allwinner_r40_realize()
510 s->memmap[AW_R40_DEV_DRAMCTL]); in allwinner_r40_realize()
[all …]
H A Daspeed_ast2600.c400 sc->memmap[ASPEED_DEV_TIMER1]); in aspeed_soc_ast2600_realize()
438 sc->memmap[ASPEED_DEV_PECI]); in aspeed_soc_ast2600_realize()
468 sc->memmap[ASPEED_DEV_SPI1 + i]); in aspeed_soc_ast2600_realize()
489 sc->memmap[ASPEED_DEV_SDMC]); in aspeed_soc_ast2600_realize()
517 sc->memmap[ASPEED_DEV_ETH1 + i]); in aspeed_soc_ast2600_realize()
536 sc->memmap[ASPEED_DEV_XDMA]); in aspeed_soc_ast2600_realize()
552 sc->memmap[ASPEED_DEV_GPIO_1_8V]); in aspeed_soc_ast2600_realize()
561 sc->memmap[ASPEED_DEV_SDHCI]); in aspeed_soc_ast2600_realize()
570 sc->memmap[ASPEED_DEV_EMMC]); in aspeed_soc_ast2600_realize()
615 sc->memmap[ASPEED_DEV_HACE]); in aspeed_soc_ast2600_realize()
[all …]
H A Dvirt-acpi-build.c128 .mmio32 = memmap[VIRT_PCIE_MMIO], in acpi_dsdt_add_pci()
129 .pio = memmap[VIRT_PCIE_PIO], in acpi_dsdt_add_pci()
130 .ecam = memmap[ecam_id], in acpi_dsdt_add_pci()
136 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; in acpi_dsdt_add_pci()
498 mem_base = vms->memmap[VIRT_MEM].base; in build_srat()
665 const MemMapEntry *memmap = vms->memmap; in build_madt() local
695 gicv = memmap[VIRT_GIC_VCPU].base; in build_madt()
696 gich = memmap[VIRT_GIC_HYP].base; in build_madt()
804 const MemMapEntry *memmap = vms->memmap; in build_dsdt() local
819 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], in build_dsdt()
[all …]
H A Dvirt.c910 hwaddr base = vms->memmap[uart].base; in create_uart()
911 hwaddr size = vms->memmap[uart].size; in create_uart()
1050 hwaddr base = vms->memmap[gpio].base; in create_gpio_devices()
1051 hwaddr size = vms->memmap[gpio].size; in create_gpio_devices()
1489 base_ecam = vms->memmap[ecam_id].base; in create_pcie()
1490 size_ecam = vms->memmap[ecam_id].size; in create_pcie()
1784 vms->memmap[i].base = region_base; in virt_set_high_memmap()
1785 vms->memmap[i].size = region_size; in virt_set_high_memmap()
1814 vms->memmap = extended_memmap; in virt_set_memmap()
1817 vms->memmap[i] = base_memmap[i]; in virt_set_memmap()
[all …]
H A Dorangepi.c73 object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_DEV_SDRAM], in orangepi_init()
92 memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_DEV_SDRAM], in orangepi_init()
100 orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM]; in orangepi_init()
H A Dbananapi_m2u.c86 r40->memmap[AW_R40_DEV_SDRAM], &error_abort); in bpim2u_init()
120 r40->memmap[AW_R40_DEV_SDRAM], machine->ram); in bpim2u_init()
122 bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM]; in bpim2u_init()
H A Daspeed_soc_common.c45 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); in aspeed_soc_uart_realize()
52 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); in aspeed_soc_uart_realize()
106 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); in aspeed_soc_dram_init()
/qemu/hw/mips/
H A Dboston.c563 memmap[BOSTON_PCIE0].base, memmap[BOSTON_PCIE0].size, in create_fdt()
564 memmap[BOSTON_PCIE0_MMIO].base, memmap[BOSTON_PCIE0_MMIO].size); in create_fdt()
567 memmap[BOSTON_PCIE1].base, memmap[BOSTON_PCIE1].size, in create_fdt()
568 memmap[BOSTON_PCIE1_MMIO].base, memmap[BOSTON_PCIE1_MMIO].size); in create_fdt()
571 memmap[BOSTON_PCIE2].base, memmap[BOSTON_PCIE2].size, in create_fdt()
572 memmap[BOSTON_PCIE2_MMIO].base, memmap[BOSTON_PCIE2_MMIO].size); in create_fdt()
580 memmap[BOSTON_GIC].size); in create_fdt()
599 memmap[BOSTON_CDMM].size); in create_fdt()
607 memmap[BOSTON_CPC].size); in create_fdt()
644 memmap[BOSTON_UART].size); in create_fdt()
[all …]
/qemu/hw/dma/
H A Dsoc_dma.c80 } *memmap; member
114 lo = dma->memmap; in soc_dma_lookup()
133 while (entry < dma->memmap + dma->memmap_size && in soc_dma_ch_update_type()
265 dma->memmap = g_realloc(dma->memmap, sizeof(*entry) * in soc_dma_port_add_fifo()
284 while (entry < dma->memmap + dma->memmap_size && in soc_dma_port_add_fifo()
297 (uint8_t *) (dma->memmap + dma->memmap_size ++) - in soc_dma_port_add_fifo()
315 dma->memmap = g_realloc(dma->memmap, sizeof(*entry) * in soc_dma_port_add_mem()
344 while (entry < dma->memmap + dma->memmap_size && in soc_dma_port_add_mem()
350 (uint8_t *) (dma->memmap + dma->memmap_size ++) - in soc_dma_port_add_mem()
/qemu/include/hw/arm/
H A Dvirt.h161 MemMapEntry *memmap; member
198 return vms->memmap[region].size / redist_size; in virt_redist_capacity()
H A Dallwinner-h3.h131 const hwaddr *memmap; member
H A Dallwinner-r40.h116 const hwaddr *memmap; member
/qemu/hw/openrisc/
H A Dopenrisc_sim.c109 const struct MemmapEntry *memmap, in openrisc_create_fdt() argument
129 memmap[OR1KSIM_DRAM].base); in openrisc_create_fdt()
132 memmap[OR1KSIM_DRAM].base, mem_size); in openrisc_create_fdt()
/qemu/include/hw/tricore/
H A Dtc27x_soc.h90 const MemmapEntry *memmap; member

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