reg_num (reference) in projects: qemu - OpenGrok search results

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Searched refs:reg_num (Results 1 – 11 of 11) sorted by relevance

/qemu/target/riscv/
H A D	translate.c	323 static TCGv get_gpr(DisasContext ctx, int reg_num, DisasExtend ext) in get_gpr() 327 if (reg_num == 0) { in get_gpr() 338 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in get_gpr() 342 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in get_gpr() 354 return cpu_gpr[reg_num]; in get_gprh() argument 357 static TCGv get_gprh(DisasContext ctx, int reg_num) in get_gprh() 360 if (reg_num == 0) { in get_gprh() 363 return cpu_gprh[reg_num]; in dest_gpr() argument 366 static TCGv dest_gpr(DisasContext ctx, int reg_num) in dest_gpr() 368 if (reg_num in dest_gpr() 320 get_gpr(DisasContext ctx,int reg_num,DisasExtend ext) get_gpr() argument 371 dest_gprh(DisasContext * ctx,int reg_num) dest_gprh() argument 379 gen_set_gpr(DisasContext * ctx,int reg_num,TCGv t) gen_set_gpr() argument 400 gen_set_gpri(DisasContext * ctx,int reg_num,target_long imm) gen_set_gpri() argument 421 gen_set_gpr128(DisasContext * ctx,int reg_num,TCGv rl,TCGv rh) gen_set_gpr128() argument 430 get_fpr_hs(DisasContext * ctx,int reg_num) get_fpr_hs() argument 457 get_fpr_d(DisasContext * ctx,int reg_num) get_fpr_d() argument 482 dest_fpr(DisasContext * ctx,int reg_num) dest_fpr() argument 505 gen_set_fpr_hs(DisasContext * ctx,int reg_num,TCGv_i64 t) gen_set_fpr_hs() argument 529 gen_set_fpr_d(DisasContext * ctx,int reg_num,TCGv_i64 t) gen_set_fpr_d() argument [all...]
/qemu/target/loongarch/tcg/
H A D	translate.c	175 if (reg_num == 0) { in gpr_src() 181 return cpu_gpr[reg_num]; in gpr_src() 184 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in gpr_src() 188 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in gpr_src() 196 if (reg_num == 0 \|\| dst_ext) { in gpr_dst() 199 return cpu_gpr[reg_num]; in gpr_dst() 204 if (reg_num != 0) { in gen_set_gpr() 207 tcg_gen_mov_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 210 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 213 tcg_gen_ext32u_tl(cpu_gpr[reg_num], t); in gen_set_gpr() [all …]
/qemu/target/riscv/insn_trans/
H A D	trans_rvzacas.c.inc	44 static TCGv_i64 get_gpr_pair(DisasContext ctx, int reg_num) 50 if (reg_num == 0) { 55 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 59 static void gen_set_gpr_pair(DisasContext ctx, int reg_num, TCGv_i64 t) 63 if (reg_num != 0) { 65 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 67 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 68 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 72 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 73 tcg_gen_sari_tl(cpu_gprh[reg_num + 1], cpu_gpr[reg_num + 1], 63);
/qemu/tests/qtest/libqos/
H A D	ahci.h	519 return ahci_mread(ahci, 4 * reg_num); in ahci_rreg() 524 ahci_mwrite(ahci, 4 * reg_num, value); in ahci_wreg() 529 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) \| mask); in ahci_set() 534 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) & ~mask); in ahci_clr() 539 return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num; in ahci_px_offset() 543 uint32_t reg_num) in ahci_px_rreg() argument 545 return ahci_rreg(ahci, ahci_px_offset(port, reg_num)); in ahci_px_rreg() 551 ahci_wreg(ahci, ahci_px_offset(port, reg_num), value); in ahci_px_wreg() 557 ahci_px_wreg(ahci, port, reg_num, in ahci_px_set() 558 ahci_px_rreg(ahci, port, reg_num) \| mask); in ahci_px_set() [all …]
/qemu/target/hexagon/
H A D	genptr.c	180 if (reg_num == HEX_REG_P3_0_ALIASED) { in gen_read_ctrl_reg() 182 } else if (reg_num == HEX_REG_PC) { in gen_read_ctrl_reg() 201 if (reg_num == HEX_REG_P3_0_ALIASED) { in gen_read_ctrl_reg_pair() 205 } else if (reg_num == HEX_REG_PC - 1) { in gen_read_ctrl_reg_pair() 223 hex_gpr[reg_num], in gen_read_ctrl_reg_pair() 224 hex_gpr[reg_num + 1]); in gen_read_ctrl_reg_pair() 247 if (reg_num == HEX_REG_P3_0_ALIASED) { in gen_write_ctrl_reg() 250 gen_log_reg_write(ctx, reg_num, val); in gen_write_ctrl_reg() 251 if (reg_num == HEX_REG_QEMU_PKT_CNT) { in gen_write_ctrl_reg() 257 if (reg_num == HEX_REG_QEMU_HVX_CNT) { in gen_write_ctrl_reg() [all …]
H A D	translate.c	`611 int reg_num = ctx->reg_log[i]; in gen_reg_writes() local 613 tcg_gen_mov_tl(hex_gpr[reg_num], get_result_gpr(ctx, reg_num)); in gen_reg_writes() 619 if (reg_num == HEX_REG_SA0) { in gen_reg_writes()`
H A D	hex_common.py	`338 self.reg_num = f"{regtype}{regid}N"`
/qemu/hw/net/can/
H A D	xlnx-versal-canfd.c	865 uint32_t reg_num) in regs2frame() argument 874 assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * in regs2frame() 877 dlc_reg_val = s->regs[reg_num + 1]; in regs2frame() 880 frame->can_id = s->regs[reg_num]; in regs2frame() 1335 uint32_t reg_num = 0; in prepare_tx_data() local 1344 temp->can_id = s->regs[reg_num]; in prepare_tx_data() 1345 temp->reg_num = reg_num; in prepare_tx_data() 1380 ((tx_ready_reg_info *)iterator->data)->reg_num); in transfer_data() 1923 int reg_num; in canfd_create_rai() local 1925 for (reg_num = 0; reg_num < num_template_to_copy; reg_num++) { in canfd_create_rai() [all …]
/qemu/hw/net/
H A D	cadence_gem.c	1490 static uint16_t gem_phy_read(CadenceGEMState s, unsigned reg_num) in gem_phy_read() argument 1492 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); in gem_phy_read() 1493 return s->phy_regs[reg_num]; in gem_phy_read() 1496 static void gem_phy_write(CadenceGEMState s, unsigned reg_num, uint16_t val) in gem_phy_write() argument 1498 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); in gem_phy_write() 1500 switch (reg_num) { in gem_phy_write() 1521 s->phy_regs[reg_num] = val; in gem_phy_write() 1527 uint32_t phy_addr, reg_num; in gem_handle_phy_access() local 1539 reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR); in gem_handle_phy_access() 1544 gem_phy_read(s, reg_num)); in gem_handle_phy_access() [all …]
/qemu/include/hw/net/
H A D	xlnx-versal-canfd.h	`84 uint32_t reg_num; member`
/qemu/hw/ide/
H A D	core.c	1283 int reg_num = addr & 7; in ide_ioport_write() local 1285 trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s); in ide_ioport_write() 1288 if (reg_num != 7 && (s->status & (BUSY_STAT\|DRQ_STAT))) { in ide_ioport_write() 1295 switch (reg_num) { in ide_ioport_write() 2226 uint32_t reg_num; in ide_ioport_read() local 2229 reg_num = addr & 7; in ide_ioport_read() 2231 switch (reg_num) { in ide_ioport_read() 2304 trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s); in ide_ioport_read()