/qemu/target/ppc/translate/ |
H A D | storage-ctrl-impl.c.inc | 146 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 247 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
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H A D | spe-impl.c.inc | 284 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
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/qemu/target/microblaze/ |
H A D | translate.c | 519 DO_TYPEBI(ori, false, tcg_gen_ori_i32) in DO_TYPEA_CFG() 1155 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP); in DO_BCC() 1202 tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set); in trans_brki() 1335 tcg_gen_ori_i32(cpu_msr, cpu_msr, imm); in do_msrclrset() 1508 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_IE); in do_rti() 1529 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_EE); in do_rte()
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/qemu/include/tcg/ |
H A D | tcg-op.h | 307 #define tcg_gen_ori_tl tcg_gen_ori_i32
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H A D | tcg-op-common.h | 87 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
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/qemu/target/sh4/ |
H A D | translate.c | 462 tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); in _decode_opc() 1253 tcg_gen_ori_i32(REG(0), REG(0), B7_0); in _decode_opc() 1262 tcg_gen_ori_i32(val, val, B7_0); in _decode_opc()
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/qemu/target/arm/tcg/ |
H A D | translate.h | 369 tcg_gen_ori_i32(p, p, bits); in set_pstate_bits()
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H A D | translate-vfp.c | 163 tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); in gen_update_fp_context() 203 tcg_gen_ori_i32(control, control, bits); in gen_update_fp_context()
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H A D | translate.c | 1398 tcg_gen_ori_i32(tmp, tmp, 2); in IWMMXT_OP() 1406 tcg_gen_ori_i32(tmp, tmp, 1); in gen_op_iwmmxt_set_cup() 3967 tcg_gen_ori_i32(tmp, tmp, a->imm << 16); in trans_MOVT()
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/qemu/tcg/ |
H A D | tcg-op.c | 421 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) in tcg_gen_ori_i32() function 1807 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); in tcg_gen_ori_i64() 1808 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); in tcg_gen_ori_i64()
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H A D | tcg-op-gvec.c | 3230 tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); in do_gvec_shifts()
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/qemu/target/xtensa/ |
H A D | translate.c | 2082 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); in translate_rsil() 2158 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm); in translate_setb_expstate() 6291 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); in translate_compare_d() 6319 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); in translate_compare_s()
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/qemu/target/m68k/ |
H A D | translate.c | 2129 tcg_gen_ori_i32(tmp, src1, mask); in DISAS_INSN() 5695 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); in DISAS_INSN()
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/qemu/target/ppc/ |
H A D | translate.c | 5175 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); in gen_tlbsx_40x() 5248 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); in gen_tlbsx_440()
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/qemu/target/i386/tcg/ |
H A D | translate.c | 2187 tcg_gen_ori_i32(t, t, mask); in gen_set_hflag()
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/qemu/target/hppa/ |
H A D | translate.c | 4179 tcg_gen_ori_i32(dst, src, INT32_MIN); in gen_fnegabs_f()
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/qemu/target/sparc/ |
H A D | translate.c | 223 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit); in gen_update_fprs_dirty()
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