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Searched refs:v7m (Results 1 – 20 of 20) sorted by relevance

/qemu/target/arm/tcg/
H A Dm_helper.c534 env->v7m.other_ss_msp = env->v7m.other_sp; in switch_v7m_security_state()
537 env->v7m.other_ss_psp = env->v7m.other_sp; in switch_v7m_security_state()
1505 !(env->v7m.ccr[env->v7m.secure] & in do_v7m_exception_exit()
2333 env->v7m.cfsr[env->v7m.secure] |= in arm_v7m_cpu_do_interrupt()
2524 return env->v7m.msplim[env->v7m.secure]; in HELPER()
2529 return env->v7m.psplim[env->v7m.secure]; in HELPER()
2531 return env->v7m.primask[env->v7m.secure]; in HELPER()
2537 return env->v7m.basepri[env->v7m.secure]; in HELPER()
2542 return env->v7m.faultmask[env->v7m.secure]; in HELPER()
2700 env->v7m.msplim[env->v7m.secure] = val & ~7; in HELPER()
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H A Dtranslate-m-nocp.c133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM()
134 sfpa = load_cpu_field(v7m.control[M_REG_S]); in trans_VSCCLRM()
187 store_cpu_field(tcg_constant_i32(0), v7m.vpr); in trans_VSCCLRM()
296 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
297 fpca = load_cpu_field(v7m.control[M_REG_S]); in gen_branch_fpInactive()
405 store_cpu_field(tmp, v7m.vpr); in gen_M_fp_sysreg_write()
412 vpr = load_cpu_field(v7m.vpr); in gen_M_fp_sysreg_write()
415 store_cpu_field(vpr, v7m.vpr); in gen_M_fp_sysreg_write()
509 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
552 tmp = load_cpu_field(v7m.vpr); in gen_M_fp_sysreg_read()
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H A Dmeson.build59 arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
60 arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
H A Dhflags.c101 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; in rebuild_hflags_m32()
123 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { in rebuild_hflags_m32()
H A Dmve_helper.c81 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { in mve_element_mask()
84 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { in mve_element_mask()
88 if (env->v7m.ltpsize < 4 && in mve_element_mask()
113 uint32_t vpr = env->v7m.vpr; in mve_advance_vpt()
148 env->v7m.vpr = vpr; in mve_advance_vpt()
2617 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ in DO_VIDUP_ALL()
2639 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
2710 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); in HELPER()
2730 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); in HELPER()
3183 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
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H A Dtranslate-vfp.c155 tmp = load_cpu_field(v7m.fpccr[M_REG_S]); in gen_update_fp_context()
161 store_cpu_field(tmp, v7m.fpccr[M_REG_S]); in gen_update_fp_context()
174 fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); in gen_update_fp_context()
177 store_cpu_field(tcg_constant_i32(0), v7m.vpr); in gen_update_fp_context()
196 control = load_cpu_field(v7m.control[M_REG_S]); in gen_update_fp_context()
198 store_cpu_field(control, v7m.control[M_REG_S]); in gen_update_fp_context()
H A Dop_helper.c140 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { in handle_possible_div0_trap()
H A Dt32.decode395 # Note that the v7m insn overlaps both the normal and banked insn.
H A Dtranslate-mve.c1328 TCGv_i32 vpr = load_cpu_field(v7m.vpr); in gen_vpst()
1349 store_cpu_field(vpr, v7m.vpr); in gen_vpst()
H A Dtranslate.c8257 store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); in trans_DLS()
8322 store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); in trans_WLS()
8402 tmp = load_cpu_field(v7m.ltpsize); in trans_LE()
8430 TCGv_i32 ltpsize = load_cpu_field(v7m.ltpsize); in trans_LE()
8444 store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); in trans_LE()
8468 store_cpu_field_constant(4, v7m.ltpsize); in trans_LCTP()
/qemu/target/arm/
H A Dmachine.c352 VMSTATE_UINT32(env.v7m.nsacr, ARMCPU),
370 VMSTATE_UINT32(env.v7m.vpr, ARMCPU),
371 VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU),
387 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
388 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
390 VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
565 VMSTATE_UINT32(env.v7m.secure, ARMCPU),
585 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU),
586 VMSTATE_UINT32(env.v7m.sfar, ARMCPU),
598 VMSTATE_UINT32(env.v7m.aircr, ARMCPU),
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H A Dgdbstub.c198 return gdb_get_reg32(buf, env->v7m.vpr); in mve_gdb_get_reg()
211 env->v7m.vpr = ldl_p(buf); in mve_gdb_set_reg()
351 ptr = &env->v7m.msplim[sec]; in m_sysreg_ptr()
354 ptr = &env->v7m.psplim[sec]; in m_sysreg_ptr()
357 ptr = &env->v7m.primask[sec]; in m_sysreg_ptr()
360 ptr = &env->v7m.basepri[sec]; in m_sysreg_ptr()
363 ptr = &env->v7m.faultmask[sec]; in m_sysreg_ptr()
366 ptr = &env->v7m.control[sec]; in m_sysreg_ptr()
395 return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); in arm_gdb_get_m_systemreg()
397 return m_sysreg_get(env, buf, reg, env->v7m.secure); in arm_gdb_get_m_systemreg()
H A Dcpu.c393 env->v7m.ltpsize = 4; in arm_cpu_reset_hold()
400 env->v7m.secure = true; in arm_cpu_reset_hold()
407 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; in arm_cpu_reset_hold()
415 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold()
423 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
448 vecbase = env->v7m.vecbase[env->v7m.secure]; in arm_cpu_reset_hold()
479 env->v7m.secure = false; in arm_cpu_reset_hold()
480 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold()
481 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; in arm_cpu_reset_hold()
482 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset_hold()
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H A DKconfig6 # translate.c v7m helpers under ARM_V7M.
H A Dinternals.h1048 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; in v7m_using_psp()
1059 return env->v7m.psplim[env->v7m.secure]; in v7m_sp_limit()
1061 return env->v7m.msplim[env->v7m.secure]; in v7m_sp_limit()
1073 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { in v7m_cpacr_pass()
H A Dcpu.h571 } v7m; member
1540 | env->v7m.exception; in xpsr_read()
2636 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2646 !(env->v7m.control[env->v7m.secure] & 1); in arm_current_el()
H A Dvfp_helper.c182 fpscr |= env->v7m.ltpsize << 16; in HELPER()
220 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, in HELPER()
H A Dhelper.c12434 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { in fp_exception_el()
12439 if (!extract32(env->v7m.nsacr, 10, 1)) { in fp_exception_el()
12563 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); in arm_mmu_idx_el()
12629 if (env->v7m.vpr) { in mve_no_pred()
12632 if (env->v7m.ltpsize < 4) { in mve_no_pred()
12656 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in cpu_get_tb_cpu_state()
12657 != env->v7m.secure) { in cpu_get_tb_cpu_state()
12661 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && in cpu_get_tb_cpu_state()
12663 (env->v7m.secure && in cpu_get_tb_cpu_state()
12674 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { in cpu_get_tb_cpu_state()
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H A Dptw.c217 switch (env->v7m.mpu_ctrl[is_secure] & in regime_translation_disabled()
2350 return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; in pmsav7_use_background_region()
/qemu/hw/intc/
H A Darmv7m_nvic.c358 if (env->v7m.primask[M_REG_NS]) { in nvic_exec_prio()
368 if (env->v7m.primask[M_REG_S]) { in nvic_exec_prio()
386 if (env->v7m.faultmask[M_REG_S]) { in nvic_exec_prio()
1240 return cpu->env.v7m.hfsr; in nvic_readl()
1242 return cpu->env.v7m.dfsr; in nvic_readl()
1256 return cpu->env.v7m.bfar; in nvic_readl()
1352 return cpu->env.v7m.nsacr; in nvic_readl()
1488 return cpu->env.v7m.sfsr; in nvic_readl()
1496 return cpu->env.v7m.sfar; in nvic_readl()
1805 cpu->env.v7m.bfar = value; in nvic_writel()
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