/qemu/target/arm/tcg/ |
H A D | m_helper.c | 534 env->v7m.other_ss_msp = env->v7m.other_sp; in switch_v7m_security_state() 537 env->v7m.other_ss_psp = env->v7m.other_sp; in switch_v7m_security_state() 1505 !(env->v7m.ccr[env->v7m.secure] & in do_v7m_exception_exit() 2333 env->v7m.cfsr[env->v7m.secure] |= in arm_v7m_cpu_do_interrupt() 2524 return env->v7m.msplim[env->v7m.secure]; in HELPER() 2529 return env->v7m.psplim[env->v7m.secure]; in HELPER() 2531 return env->v7m.primask[env->v7m.secure]; in HELPER() 2537 return env->v7m.basepri[env->v7m.secure]; in HELPER() 2542 return env->v7m.faultmask[env->v7m.secure]; in HELPER() 2700 env->v7m.msplim[env->v7m.secure] = val & ~7; in HELPER() [all …]
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H A D | translate-m-nocp.c | 133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM() 134 sfpa = load_cpu_field(v7m.control[M_REG_S]); in trans_VSCCLRM() 187 store_cpu_field(tcg_constant_i32(0), v7m.vpr); in trans_VSCCLRM() 296 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive() 297 fpca = load_cpu_field(v7m.control[M_REG_S]); in gen_branch_fpInactive() 405 store_cpu_field(tmp, v7m.vpr); in gen_M_fp_sysreg_write() 412 vpr = load_cpu_field(v7m.vpr); in gen_M_fp_sysreg_write() 415 store_cpu_field(vpr, v7m.vpr); in gen_M_fp_sysreg_write() 509 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read() 552 tmp = load_cpu_field(v7m.vpr); in gen_M_fp_sysreg_read() [all …]
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H A D | meson.build | 59 arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) 60 arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
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H A D | hflags.c | 101 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; in rebuild_hflags_m32() 123 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { in rebuild_hflags_m32()
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H A D | mve_helper.c | 81 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { in mve_element_mask() 84 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { in mve_element_mask() 88 if (env->v7m.ltpsize < 4 && in mve_element_mask() 113 uint32_t vpr = env->v7m.vpr; in mve_advance_vpt() 148 env->v7m.vpr = vpr; in mve_advance_vpt() 2617 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ in DO_VIDUP_ALL() 2639 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2710 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); in HELPER() 2730 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); in HELPER() 3183 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ [all …]
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H A D | translate-vfp.c | 155 tmp = load_cpu_field(v7m.fpccr[M_REG_S]); in gen_update_fp_context() 161 store_cpu_field(tmp, v7m.fpccr[M_REG_S]); in gen_update_fp_context() 174 fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); in gen_update_fp_context() 177 store_cpu_field(tcg_constant_i32(0), v7m.vpr); in gen_update_fp_context() 196 control = load_cpu_field(v7m.control[M_REG_S]); in gen_update_fp_context() 198 store_cpu_field(control, v7m.control[M_REG_S]); in gen_update_fp_context()
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H A D | op_helper.c | 140 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { in handle_possible_div0_trap()
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H A D | t32.decode | 395 # Note that the v7m insn overlaps both the normal and banked insn.
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H A D | translate-mve.c | 1328 TCGv_i32 vpr = load_cpu_field(v7m.vpr); in gen_vpst() 1349 store_cpu_field(vpr, v7m.vpr); in gen_vpst()
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H A D | translate.c | 8257 store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); in trans_DLS() 8322 store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); in trans_WLS() 8402 tmp = load_cpu_field(v7m.ltpsize); in trans_LE() 8430 TCGv_i32 ltpsize = load_cpu_field(v7m.ltpsize); in trans_LE() 8444 store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); in trans_LE() 8468 store_cpu_field_constant(4, v7m.ltpsize); in trans_LCTP()
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/qemu/target/arm/ |
H A D | machine.c | 352 VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), 370 VMSTATE_UINT32(env.v7m.vpr, ARMCPU), 371 VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), 387 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 388 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 390 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 565 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 585 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), 586 VMSTATE_UINT32(env.v7m.sfar, ARMCPU), 598 VMSTATE_UINT32(env.v7m.aircr, ARMCPU), [all …]
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H A D | gdbstub.c | 198 return gdb_get_reg32(buf, env->v7m.vpr); in mve_gdb_get_reg() 211 env->v7m.vpr = ldl_p(buf); in mve_gdb_set_reg() 351 ptr = &env->v7m.msplim[sec]; in m_sysreg_ptr() 354 ptr = &env->v7m.psplim[sec]; in m_sysreg_ptr() 357 ptr = &env->v7m.primask[sec]; in m_sysreg_ptr() 360 ptr = &env->v7m.basepri[sec]; in m_sysreg_ptr() 363 ptr = &env->v7m.faultmask[sec]; in m_sysreg_ptr() 366 ptr = &env->v7m.control[sec]; in m_sysreg_ptr() 395 return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); in arm_gdb_get_m_systemreg() 397 return m_sysreg_get(env, buf, reg, env->v7m.secure); in arm_gdb_get_m_systemreg()
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H A D | cpu.c | 393 env->v7m.ltpsize = 4; in arm_cpu_reset_hold() 400 env->v7m.secure = true; in arm_cpu_reset_hold() 407 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; in arm_cpu_reset_hold() 415 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold() 423 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold() 448 vecbase = env->v7m.vecbase[env->v7m.secure]; in arm_cpu_reset_hold() 479 env->v7m.secure = false; in arm_cpu_reset_hold() 480 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold() 481 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; in arm_cpu_reset_hold() 482 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset_hold() [all …]
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H A D | Kconfig | 6 # translate.c v7m helpers under ARM_V7M.
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H A D | internals.h | 1048 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; in v7m_using_psp() 1059 return env->v7m.psplim[env->v7m.secure]; in v7m_sp_limit() 1061 return env->v7m.msplim[env->v7m.secure]; in v7m_sp_limit() 1073 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { in v7m_cpacr_pass()
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H A D | cpu.h | 571 } v7m; member 1540 | env->v7m.exception; in xpsr_read() 2636 return env->v7m.exception != 0; in arm_v7m_is_handler_mode() 2646 !(env->v7m.control[env->v7m.secure] & 1); in arm_current_el()
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H A D | vfp_helper.c | 182 fpscr |= env->v7m.ltpsize << 16; in HELPER() 220 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, in HELPER()
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H A D | helper.c | 12434 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { in fp_exception_el() 12439 if (!extract32(env->v7m.nsacr, 10, 1)) { in fp_exception_el() 12563 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); in arm_mmu_idx_el() 12629 if (env->v7m.vpr) { in mve_no_pred() 12632 if (env->v7m.ltpsize < 4) { in mve_no_pred() 12656 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in cpu_get_tb_cpu_state() 12657 != env->v7m.secure) { in cpu_get_tb_cpu_state() 12661 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && in cpu_get_tb_cpu_state() 12663 (env->v7m.secure && in cpu_get_tb_cpu_state() 12674 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { in cpu_get_tb_cpu_state() [all …]
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H A D | ptw.c | 217 switch (env->v7m.mpu_ctrl[is_secure] & in regime_translation_disabled() 2350 return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; in pmsav7_use_background_region()
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/qemu/hw/intc/ |
H A D | armv7m_nvic.c | 358 if (env->v7m.primask[M_REG_NS]) { in nvic_exec_prio() 368 if (env->v7m.primask[M_REG_S]) { in nvic_exec_prio() 386 if (env->v7m.faultmask[M_REG_S]) { in nvic_exec_prio() 1240 return cpu->env.v7m.hfsr; in nvic_readl() 1242 return cpu->env.v7m.dfsr; in nvic_readl() 1256 return cpu->env.v7m.bfar; in nvic_readl() 1352 return cpu->env.v7m.nsacr; in nvic_readl() 1488 return cpu->env.v7m.sfsr; in nvic_readl() 1496 return cpu->env.v7m.sfar; in nvic_readl() 1805 cpu->env.v7m.bfar = value; in nvic_writel() [all …]
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