| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
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| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1922 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1925 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1894 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1897 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1921 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1924 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1921 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1924 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1894 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1897 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1894 Register BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1897 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1883 unsigned BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1886 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1849 unsigned BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1852 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1081 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
1098 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
1099 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1839 unsigned BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint() local
1842 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB) in areMemAccessesTriviallyDisjoint()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 104 unsigned BaseRegA = 0, BaseRegB = 0; in areMemAccessesTriviallyDisjoint() local
108 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
109 if (BaseRegA == BaseRegB) { in areMemAccessesTriviallyDisjoint()
|