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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h199 return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()
211 return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC); in isVGPRClass()
216 return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC); in isAGPRClass()
221 return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC); in isVectorSuperClass()
226 return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC); in isVSSuperClass()
230 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs() argument
231 return RC->TSFlags & SIRCFlags::HasVGPR; in hasVGPRs()
236 return RC->TSFlags & SIRCFlags::HasAGPR; in hasAGPRs()
241 return RC->TSFlags & SIRCFlags::HasSGPR; in hasSGPRs()
246 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
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H A DGCNRewritePartialRegUses.cpp81 const TargetRegisterClass *RC; member
210 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask() local
211 if (RC->isAllocatable() && TRI->isRegClassAligned(RC, AlignNumBits)) in getAllocatableAndAlignedRegClassMask()
271 auto *RC = TRI->getRegClass(ClassID); in getRegClassWithShiftedSubregs() local
272 unsigned NumBits = TRI->getRegSizeInBits(*RC); in getRegClassWithShiftedSubregs()
275 MinRC = RC; in getRegClassWithShiftedSubregs()
290 return (MinRC != RC || RShift != 0) ? MinRC : nullptr; in getRegClassWithShiftedSubregs()
418 auto *RC = MRI->getRegClass(Reg); in rewriteReg() local
431 const TargetRegisterClass *&SubRegRC = I->second.RC; in rewriteReg()
434 SubRegRC = TRI->getSubRegisterClass(RC, SubReg); in rewriteReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp89 if (RC == &WebAssembly::I32RegClass) in getDropOpcode()
91 if (RC == &WebAssembly::I64RegClass) in getDropOpcode()
93 if (RC == &WebAssembly::F32RegClass) in getDropOpcode()
95 if (RC == &WebAssembly::F64RegClass) in getDropOpcode()
108 if (RC == &WebAssembly::I32RegClass) in getLocalGetOpcode()
110 if (RC == &WebAssembly::I64RegClass) in getLocalGetOpcode()
112 if (RC == &WebAssembly::F32RegClass) in getLocalGetOpcode()
114 if (RC == &WebAssembly::F64RegClass) in getLocalGetOpcode()
127 if (RC == &WebAssembly::I32RegClass) in getLocalSetOpcode()
129 if (RC == &WebAssembly::I64RegClass) in getLocalSetOpcode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp93 unsigned ID = RC.getID(); in mask()
119 if (RC.contains(Reg)) in getPhysRegBitWidth()
133 return RC; in composeWithSubRegIndex()
142 switch (RC.getID()) { in composeWithSubRegIndex()
278 return eXTR(RC, 0, RW); in evaluate()
283 uint16_t W = RC.width(); in evaluate()
304 return RC; in evaluate()
696 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
798 RegisterCell RC(WR); in evaluate() local
894 RegisterCell RC(W0); in evaluate() local
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H A DBitTracker.h327 return !operator==(RC);
365 RegisterCell RC(Width); in self()
368 return RC; in self()
373 RegisterCell RC(Width); in top()
376 return RC; in top()
382 RegisterCell RC(W); in ref()
384 RC[i] = BitValue::ref(C[i]); in ref()
385 return RC; in ref()
406 RegisterCell RC = getCell(RR, M); in getRef() local
407 return RegisterCell::ref(RC); in getRef()
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/freebsd/contrib/ofed/libibverbs/
H A Dopcode.h83 IBV_OPCODE(RC, SEND_FIRST),
84 IBV_OPCODE(RC, SEND_MIDDLE),
85 IBV_OPCODE(RC, SEND_LAST),
87 IBV_OPCODE(RC, SEND_ONLY),
89 IBV_OPCODE(RC, RDMA_WRITE_FIRST),
90 IBV_OPCODE(RC, RDMA_WRITE_MIDDLE),
91 IBV_OPCODE(RC, RDMA_WRITE_LAST),
93 IBV_OPCODE(RC, RDMA_WRITE_ONLY),
100 IBV_OPCODE(RC, ACKNOWLEDGE),
102 IBV_OPCODE(RC, COMPARE_SWAP),
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
81 (ins RC:$src1, RC:$src2, RC:$src3),
182 (ins RC:$src1, RC:$src2, RC:$src3),
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
203 (ins RC:$src1, RC:$src2, RC:$src3),
223 (ins RC:$src1, RC:$src2, RC:$src3),
395 (ins RC:$src1, RC:$src2, RC:$src3),
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H A DX86InstrAVX512.td533 Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
1616 (ins _.RC:$src2, _.RC:$src3),
1618 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1, _.RC:$src3)), 1>,
1740 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3)), 1>,
3903 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))],
3916 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
5223 _.RC:$src1, _.RC:$src2)>;
6550 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
6551 (_.VT (MaskOpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)), 1, 1>,
7175 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp30 if (RC == &NVPTX::Float32RegsRegClass) in getNVPTXRegClassName()
32 if (RC == &NVPTX::Float64RegsRegClass) in getNVPTXRegClassName()
34 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassName()
54 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassName()
56 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassName()
58 if (RC == &NVPTX::Int1RegsRegClass) in getNVPTXRegClassName()
60 if (RC == &NVPTX::SpecialRegsRegClass) in getNVPTXRegClassName()
70 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassStr()
72 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassStr()
74 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassStr()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h75 void compute(const TargetRegisterClass *RC) const;
78 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
79 const RCInfo &RCI = RegClass[RC->getID()]; in get()
81 compute(RC); in get()
95 return get(RC).NumRegs; in getNumAllocatableRegs()
102 return get(RC); in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
112 return get(RC).ProperSubClass; in isProperSubClass()
127 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost() argument
128 return get(RC).MinCost; in getMinCost()
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H A DTargetRegisterInfo.h125 return RC != this && hasSubClassEq(RC); in hasSubClass()
130 unsigned ID = RC->getID(); in hasSubClassEq()
137 return RC->hasSubClass(this); in hasSuperClass()
142 return RC->hasSubClassEq(this); in hasSuperClassEq()
293 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
330 vt_iterator I = legalclasstypes_begin(RC); in legalclasstypes_end()
651 return RC; in getSubClassWithSubReg()
821 return RC; in getCrossCopyRegClass()
833 return RC; in getLargestLegalSuperClass()
858 const TargetRegisterClass *RC) const = 0;
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/freebsd/sys/ofed/include/rdma/
H A Dib_pack.h115 IB_OPCODE(RC, SEND_FIRST),
116 IB_OPCODE(RC, SEND_MIDDLE),
117 IB_OPCODE(RC, SEND_LAST),
119 IB_OPCODE(RC, SEND_ONLY),
121 IB_OPCODE(RC, RDMA_WRITE_FIRST),
122 IB_OPCODE(RC, RDMA_WRITE_MIDDLE),
123 IB_OPCODE(RC, RDMA_WRITE_LAST),
125 IB_OPCODE(RC, RDMA_WRITE_ONLY),
132 IB_OPCODE(RC, ACKNOWLEDGE),
134 IB_OPCODE(RC, COMPARE_SWAP),
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp73 if (llvm::is_contained(RCs, RC)) in addRegisterClass()
85 RCsWithLargestRegSize[M] = RC; in addRegisterClass()
87 RC->RSI.get(M).SpillSize) in addRegisterClass()
88 RCsWithLargestRegSize[M] = RC; in addRegisterClass()
92 RCs.emplace_back(RC); in addRegisterClass()
179 if (!VisitedRCs.insert(RC).second) in visitRegisterBankClasses()
183 VisitFn(RC, Kind.str()); in visitRegisterBankClasses()
190 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass)) in visitRegisterBankClasses()
204 if (BV.test(RC->EnumValue)) { in visitRegisterBankClasses()
227 RCsGroupedByWord[RC->EnumValue / 32].push_back(RC); in emitBaseClassImplementation()
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H A DRegisterInfoEmitter.cpp149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
221 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
1066 if (RC.RSI.isSimple()) in runMCDesc()
1069 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1177 if (llvm::any_of(RegisterClasses, [](const auto &RC) { return RC.getBaseClassOrder(); })) { in runTargetHeader() argument
1227 if (RC.Allocatable) in runTargetDesc()
1294 << RC.getName() << '\n'; in runTargetDesc()
1411 printMask(OS, RC.LaneMask); in runTargetDesc()
1585 if (RC.getBaseClassOrder()) in runTargetDesc()
1586 BaseClasses.push_back(&RC); in runTargetDesc()
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H A DCodeGenRegisters.cpp993 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
1022 if (&*I == &RC) in computeSubClasses()
1212 getReg(RC); in CodeGenRegBank()
1360 return RC; in getRegClass()
1979 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) in computeRegUnitSets()
2300 RC->setSubClassWithSubReg(&SubIdx, RC); in inferSubClassWithSubReg()
2329 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
2377 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" + in inferMatchingSuperRegClass()
2445 FoundRC = &RC; in getRegClassForRegister()
2481 RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC))) in getMinimalPhysRegClass()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp197 if (!RC || RC->isAllocatable()) in getAllocatableClass()
198 return RC; in getAllocatableClass()
222 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
223 BestRC = RC; in getMinimalPhysRegClass()
239 if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) && in getMinimalPhysRegClassLLT()
241 BestRC = RC; in getMinimalPhysRegClassLLT()
260 if (RC) { in getAllocatableSet()
356 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
369 BestRC = RC; in getCommonSuperRegClass()
519 RC = MRI.getRegClass(Reg); in getRegSizeInBits()
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H A DRegisterClassInfo.cpp127 assert(RC && "no register class given"); in compute()
128 RCInfo &RCI = RegClass[RC->getID()]; in compute()
132 unsigned NumRegs = RC->getNumRegs(); in compute()
182 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
204 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
218 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
219 RC = C; in computePSetLimit()
223 assert(RC && "Failed to find register class"); in computePSetLimit()
224 compute(RC); in computePSetLimit()
225 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); in computePSetLimit()
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H A DRegisterBank.cpp26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
28 if (!covers(RC)) in verify()
39 if (!RC.hasSubClassEq(&SubRC)) in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
53 return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0; in covers()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
94 if (covers(RC)) in print()
95 OS << LS << TRI->getRegClassName(&RC); in print()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
273 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
274 [(set RC:$dst, (MipsCMovFP_T RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,
278 PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
303 PseudoSE<(outs RC:$dst1, RC:$dst2),
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H A DMipsInstrFPU.td113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
204 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
206 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
211 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
213 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
260 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
986 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
987 (Nmadd RC:$fr, RC:$fs, RC:$ft)>;
988 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)),
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
47 if (LC && RC) { in FoldBinOp()
49 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
59 if (LC && RC) { in FoldExactBinOp()
61 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
72 if (LC && RC) { in FoldNoWrapBinOp()
100 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local
101 if (LC && RC) in FoldICmp()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DCGSCCPassManager.cpp187 RCWorklist.insert(&RC); in run()
608 for (auto &C : RC) { in invalidate()
879 RefSCC *RC = &InitialRC; in updateCGAndAnalysisManagerForPass() local
960 assert((RC == &TargetRC || in updateCGAndAnalysisManagerForPass()
973 assert((RC == &TargetRC || in updateCGAndAnalysisManagerForPass()
1019 if (&TargetRC == RC) in updateCGAndAnalysisManagerForPass()
1041 RC = &C->getOuterRefSCC(); in updateCGAndAnalysisManagerForPass()
1067 if (&TargetRC != RC) { in updateCGAndAnalysisManagerForPass()
1103 if (&TargetRC != RC) { in updateCGAndAnalysisManagerForPass()
1121 auto InitialSCCIndex = RC->find(*C) - RC->begin(); in updateCGAndAnalysisManagerForPass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td136 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
241 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
378 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
449 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
587 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>;
599 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>;
615 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;
628 (ins RC:$vy, RC:$vz, I64:$sy)>;
631 (ins RC:$vy, RC:$vz, uimm7:$sy)>;
657 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 if (LC && RC) { in FoldBinOp()
60 return Fold(ConstantExpr::get(Opc, LC, RC)); in FoldBinOp()
61 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldBinOp()
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
70 if (LC && RC) { in FoldExactBinOp()
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
83 if (LC && RC) { in FoldNoWrapBinOp()
104 auto *RC = dyn_cast<Constant>(RHS); in FoldICmp() local
105 if (LC && RC) in FoldICmp()
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