| /dragonfly/sys/dev/drm/i915/ |
| H A D | i915_sysfs.c | 295 struct intel_rps *rps = &dev_priv->gt_pm.rps;
305 if (val < rps->min_freq || val > rps->max_freq)
309 rps->boost_freq = val;
339 struct intel_rps *rps = &dev_priv->gt_pm.rps;
353 if (val < rps->min_freq ||
354 val > rps->max_freq ||
361 if (val > rps->rp0_freq)
397 struct intel_rps *rps = &dev_priv->gt_pm.rps;
411 if (val < rps->min_freq ||
412 val > rps->max_freq ||
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| H A D | intel_pm.c | 6533 rps->max_freq = rps->rp0_freq; in gen6_init_rps_frequencies()
6535 rps->efficient_freq = rps->rp1_freq; in gen6_init_rps_frequencies()
7164 rps->rp0_freq = rps->max_freq; in valleyview_init_gt_powersave()
7209 rps->rp0_freq = rps->max_freq; in cherryview_init_gt_powersave()
7229 WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq | in cherryview_init_gt_powersave()
7923 rps->idle_freq = rps->min_freq; in intel_init_gt_powersave()
7924 rps->cur_freq = rps->idle_freq; in intel_init_gt_powersave()
7926 rps->max_freq_softlimit = rps->max_freq; in intel_init_gt_powersave()
7927 rps->min_freq_softlimit = rps->min_freq; in intel_init_gt_powersave()
7950 rps->boost_freq = rps->max_freq; in intel_init_gt_powersave()
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| H A D | i915_irq.c | 413 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_enable_rps_interrupts() local
429 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_disable_rps_interrupts() local
1126 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei)); in gen6_rps_reset_ei()
1131 struct intel_rps *rps = &dev_priv->gt_pm.rps; in vlv_wa_c0_ei() local
1165 rps->ei = now; in vlv_wa_c0_ei()
1173 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_pm_rps_work() local
1214 if (rps->cur_freq > rps->efficient_freq) in gen6_pm_rps_work()
1216 else if (rps->cur_freq > rps->min_freq_softlimit) in gen6_pm_rps_work()
1241 rps->last_adj = 0; in gen6_pm_rps_work()
1732 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_irq_handler() local
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| H A D | i915_guc_submission.c | 1034 struct intel_rps *rps = &dev_priv->gt_pm.rps; in guc_interrupts_capture() local
1071 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; in guc_interrupts_capture()
1072 rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; in guc_interrupts_capture()
1077 struct intel_rps *rps = &dev_priv->gt_pm.rps; in guc_interrupts_release() local
1096 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; in guc_interrupts_release()
1097 rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; in guc_interrupts_release()
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| H A D | intel_drv.h | 1241 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz; in gen6_sanitize_rps_pm_mask()
1878 struct intel_rps_client *rps);
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| H A D | i915_gem_request.c | 419 atomic_dec(&request->i915->gt_pm.rps.num_waiters); in i915_gem_request_retire()
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| H A D | i915_drv.h | 1386 struct intel_rps rps; member
3757 struct intel_rps_client *rps);
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | rs780_dpm.c | 36 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
734 if (r600_is_uvd_state(rps->class, rps->class2)) { in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
744 rdev->pm.dpm.uvd_ps = rps; in rs780_parse_pplib_non_clock_info()
748 struct radeon_ps *rps, in rs780_parse_pplib_clock_info() argument
938 struct radeon_ps *rps) in rs780_dpm_print_power_state() argument
942 r600_dpm_print_class_info(rps->class, rps->class2); in rs780_dpm_print_power_state()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
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| H A D | trinity_dpm.c | 903 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
1078 pi->current_rps = *rps; in trinity_update_current_ps()
1084 struct radeon_ps *rps) in trinity_update_requested_ps() argument
1089 pi->requested_rps = *rps; in trinity_update_requested_ps()
1189 struct radeon_ps *rps) in trinity_setup_nbp_sim() argument
1483 if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) { in trinity_adjust_uvd_state()
1700 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1701 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
2021 r600_dpm_print_class_info(rps->class, rps->class2); in trinity_dpm_print_power_state()
2023 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
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| H A D | sumo_dpm.c | 388 struct radeon_ps *rps) in sumo_program_at() argument
988 struct radeon_ps *rps) in sumo_force_nbp_state() argument
1189 pi->current_rps = *rps; in sumo_update_current_ps()
1200 pi->requested_rps = *rps; in sumo_update_requested_ps()
1420 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1421 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1797 struct radeon_ps *rps) in sumo_dpm_print_power_state() argument
1802 r600_dpm_print_class_info(rps->class, rps->class2); in sumo_dpm_print_power_state()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| H A D | rv770_dpm.c | 54 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
2161 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2162 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2165 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv7xx_parse_pplib_non_clock_info()
2166 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2173 rdev->pm.dpm.boot_ps = rps; in rv7xx_parse_pplib_non_clock_info()
2175 rdev->pm.dpm.uvd_ps = rps; in rv7xx_parse_pplib_non_clock_info()
2437 struct radeon_ps *rps) in rv770_dpm_print_power_state() argument
2442 r600_dpm_print_class_info(rps->class, rps->class2); in rv770_dpm_print_power_state()
2444 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
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| H A D | rv6xx_dpm.c | 39 struct rv6xx_ps *ps = rps->ps_priv; in rv6xx_get_ps()
1796 struct radeon_ps *rps, in rv6xx_parse_pplib_non_clock_info() argument
1803 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv6xx_parse_pplib_non_clock_info()
1807 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
1808 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
1812 rdev->pm.dpm.boot_ps = rps; in rv6xx_parse_pplib_non_clock_info()
1814 rdev->pm.dpm.uvd_ps = rps; in rv6xx_parse_pplib_non_clock_info()
2008 struct radeon_ps *rps) in rv6xx_dpm_print_power_state() argument
2013 r600_dpm_print_class_info(rps->class, rps->class2); in rv6xx_dpm_print_power_state()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
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| H A D | ni_dpm.c | 786 struct radeon_ps *rps) in ni_apply_state_adjust_rules() argument
3560 struct radeon_ps *rps) in ni_update_current_ps() argument
3566 eg_pi->current_rps = *rps; in ni_update_current_ps()
3572 struct radeon_ps *rps) in ni_update_requested_ps() argument
3904 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in ni_parse_pplib_non_clock_info()
3908 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
3909 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
3915 rdev->pm.dpm.uvd_ps = rps; in ni_parse_pplib_non_clock_info()
4284 r600_dpm_print_class_info(rps->class, rps->class2); in ni_dpm_print_power_state()
4286 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
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| H A D | kv_dpm.c | 1136 struct radeon_ps *rps) in kv_update_current_ps() argument
1141 pi->current_rps = *rps; in kv_update_current_ps()
1147 struct radeon_ps *rps) in kv_update_requested_ps() argument
1152 pi->requested_rps = *rps; in kv_update_requested_ps()
2580 struct radeon_ps *rps, in kv_parse_pplib_non_clock_info() argument
2594 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2595 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2599 rdev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2603 rdev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2849 r600_dpm_print_class_info(rps->class, rps->class2); in kv_dpm_print_power_state()
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| H A D | btc_dpm.c | 2093 struct radeon_ps *rps) in btc_apply_state_adjust_rules() argument
2095 struct rv7xx_ps *ps = rv770_get_ps(rps); in btc_apply_state_adjust_rules()
2256 struct radeon_ps *rps) in btc_update_current_ps() argument
2258 struct rv7xx_ps *new_ps = rv770_get_ps(rps); in btc_update_current_ps()
2261 eg_pi->current_rps = *rps; in btc_update_current_ps()
2267 struct radeon_ps *rps) in btc_update_requested_ps() argument
2272 eg_pi->requested_rps = *rps; in btc_update_requested_ps()
2735 struct rv7xx_ps *ps = rv770_get_ps(rps); in btc_dpm_debugfs_print_current_performance_level()
2750 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in btc_dpm_debugfs_print_current_performance_level()
2760 struct rv7xx_ps *ps = rv770_get_ps(rps); in btc_dpm_get_current_sclk()
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| H A D | ci_dpm.c | 830 struct radeon_ps *rps) in ci_apply_state_adjust_rules() argument
839 if (rps->vce_active) { in ci_apply_state_adjust_rules()
843 rps->evclk = 0; in ci_apply_state_adjust_rules()
844 rps->ecclk = 0; in ci_apply_state_adjust_rules()
882 if (rps->vce_active) { in ci_apply_state_adjust_rules()
5143 pi->current_rps = *rps; in ci_update_current_ps()
5154 pi->requested_rps = *rps; in ci_update_requested_ps()
5493 rps->vclk = 0; in ci_parse_pplib_non_clock_info()
5494 rps->dclk = 0; in ci_parse_pplib_non_clock_info()
5978 r600_dpm_print_class_info(rps->class, rps->class2); in ci_dpm_print_power_state()
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| H A D | si_dpm.c | 2967 struct radeon_ps *rps) in si_apply_state_adjust_rules() argument
3005 if (rps->vce_active) { in si_apply_state_adjust_rules()
3008 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3011 rps->evclk = 0; in si_apply_state_adjust_rules()
3012 rps->ecclk = 0; in si_apply_state_adjust_rules()
3019 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
3095 if (rps->vce_active) { in si_apply_state_adjust_rules()
6714 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info()
6718 rps->vclk = 0; in si_parse_pplib_non_clock_info()
6719 rps->dclk = 0; in si_parse_pplib_non_clock_info()
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| H A D | ni_dpm.h | 237 struct radeon_ps *rps);
239 struct radeon_ps *rps);
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| H A D | r600_dpm.h | 134 struct radeon_ps *rps);
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| H A D | r600_dpm.c | 145 struct radeon_ps *rps) in r600_dpm_print_ps_status() argument
148 if (rps == rdev->pm.dpm.current_ps) in r600_dpm_print_ps_status()
150 if (rps == rdev->pm.dpm.requested_ps) in r600_dpm_print_ps_status()
152 if (rps == rdev->pm.dpm.boot_ps) in r600_dpm_print_ps_status()
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| H A D | rv730_dpm.c | 37 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | si_dpm.c | 3467 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3470 rps->evclk = 0; in si_apply_state_adjust_rules()
3471 rps->ecclk = 0; in si_apply_state_adjust_rules()
3478 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
7115 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info()
7119 rps->vclk = 0; in si_parse_pplib_non_clock_info()
7120 rps->dclk = 0; in si_parse_pplib_non_clock_info()
7495 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
7900 amdgpu_dpm_print_class_info(rps->class, rps->class2); in si_dpm_print_power_state()
7902 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_print_power_state()
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| H A D | amdgpu_dpm.h | 323 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ argument
324 …((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
470 struct amdgpu_ps *rps);
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| H A D | amdgpu_dpm.c | 107 struct amdgpu_ps *rps) in amdgpu_dpm_print_ps_status() argument
110 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
112 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
114 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
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| /dragonfly/sys/dev/drm/amd/include/ |
| H A D | kgd_pp_interface.h | 210 void *rps,
|