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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/IR/
H A DIntrinsicsPowerPC.td1023 def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">;
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dvector-rotates.ll38 ; CHECK-P8-NEXT: vrlh v2, v2, v3
46 ; CHECK-P7-NEXT: vrlh v2, v2, v3
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Analysis/TypeBasedAliasAnalysis/
H A Ddynamic-indices.ll12 ; CHECK: define void @vrlh(
18 define void @vrlh(%union.vector_t* %va, %union.vector_t* %vb, %union.vector_t* %vd) nounwind {
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td694 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dvector-rotates.ll38 ; CHECK-P8-NEXT: vrlh v2, v2, v3
46 ; CHECK-P7-NEXT: vrlh v2, v2, v3
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/
H A DPPCInstrAltivec.td694 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
/dports/graphics/llvm-mesa/llvm-13.0.1.src/include/llvm/IR/
H A DIntrinsicsPowerPC.td1023 def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">;
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s574 # CHECK-BE: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44]
575 # CHECK-LE: vrlh 2, 3, 4 # encoding: [0x44,0x20,0x43,0x10]
576 vrlh 2, 3, 4
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Analysis/TypeBasedAliasAnalysis/
H A Ddynamic-indices.ll12 ; CHECK: define void @vrlh(
18 define void @vrlh(%union.vector_t* %va, %union.vector_t* %vb, %union.vector_t* %vd) nounwind {
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td694 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/include/llvm/IR/
H A DIntrinsicsPowerPC.td1023 def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">;
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dvector-rotates.ll38 ; CHECK-P8-NEXT: vrlh v2, v2, v3
46 ; CHECK-P7-NEXT: vrlh v2, v2, v3
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s574 # CHECK-BE: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44]
575 # CHECK-LE: vrlh 2, 3, 4 # encoding: [0x44,0x20,0x43,0x10]
576 vrlh 2, 3, 4
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Analysis/TypeBasedAliasAnalysis/
H A Ddynamic-indices.ll12 ; CHECK: define void @vrlh(
18 define void @vrlh(%union.vector_t* %va, %union.vector_t* %vb, %union.vector_t* %vd) nounwind {
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td694 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/include/llvm/IR/
H A DIntrinsicsPowerPC.td1023 def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">;
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Analysis/TypeBasedAliasAnalysis/
H A Ddynamic-indices.ll12 ; CHECK: define void @vrlh(
18 define void @vrlh(%union.vector_t* %va, %union.vector_t* %vb, %union.vector_t* %vd) nounwind {
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s574 # CHECK-BE: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44]
575 # CHECK-LE: vrlh 2, 3, 4 # encoding: [0x44,0x20,0x43,0x10]
576 vrlh 2, 3, 4
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dvector-rotates.ll38 ; CHECK-P8-NEXT: vrlh v2, v2, v3
46 ; CHECK-P7-NEXT: vrlh v2, v2, v3
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s574 # CHECK-BE: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44]
575 # CHECK-LE: vrlh 2, 3, 4 # encoding: [0x44,0x20,0x43,0x10]
576 vrlh 2, 3, 4
/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td453 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
H A DPPCSchedule.td455 // vrlh VecGeneral
/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/include/llvm/
H A DIntrinsics.gen304 ppc_altivec_vrlh, // llvm.ppc.altivec.vrlh
1175 "llvm.ppc.altivec.vrlh",
2942 if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vrlh", 21)) return Intrinsic::ppc_altivec_vrlh;
4902 case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh
6951 case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh
H A DIntrinsicsPowerPC.td444 def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">;
/dports/games/supertux2/SuperTux-v0.6.3-Source/contrib/
H A Dschroedingers-boxes-pr-390.patch3723 zw{g+>vrlh~Yo9mLVrgUGqaJ0%gmkTuxk%k<&JTSw>V_85RM1_vXbWuL&=FzTj1qo}

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