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Searched refs:RD4 (Results 1 – 25 of 84) sorted by path

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/freebsd/sys/arm/allwinner/
H A Daw_sid.c232 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
319 while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ) in aw_sid_get_fuse()
321 val = RD4(sc, SID_RDKEY); in aw_sid_get_fuse()
323 val = RD4(sc, sc->sid_conf->efuses[i].base + in aw_sid_get_fuse()
H A Daw_thermal.c374 #define RD4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
418 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); in aw_thermal_init()
419 WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL); in aw_thermal_init()
422 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL); in aw_thermal_init()
432 val = RD4(sc, THS_DATA0 + (sensor * 4)); in aw_thermal_gettemp()
442 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); in aw_thermal_getshut()
453 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); in aw_thermal_setshut()
464 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_gethyst()
475 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_getalarm()
486 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_setalarm()
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H A Daw_usb3phy.c106 #define RD4(res, o) bus_read_4(res, (o)) macro
123 val = RD4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL); in awusb3phy_phy_enable()
131 val = RD4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL); in awusb3phy_phy_enable()
137 val = RD4(sc->res, USB3PHY_APP); in awusb3phy_phy_enable()
145 val = RD4(sc->res, USB3PHY_PHY_TUNE_HIGH); in awusb3phy_phy_enable()
H A Daw_usbphy.c162 #define RD4(res, o) bus_read_4(res, (o)) macro
164 #define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
165 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
H A Dif_awg.c336 val = RD4(sc, EMAC_RX_CTL_0); in awg_miibus_statchg()
476 tx = RD4(sc, EMAC_TX_CTL_0); in awg_enable_mac()
477 rx = RD4(sc, EMAC_RX_CTL_0); in awg_enable_mac()
566 val = RD4(sc, EMAC_TX_CTL_1); in awg_init_dma()
570 val = RD4(sc, EMAC_RX_CTL_1); in awg_init_dma()
582 val = RD4(sc, EMAC_TX_CTL_1); in awg_stop_dma()
591 val = RD4(sc, EMAC_TX_CTL_1); in awg_stop_dma()
595 val = RD4(sc, EMAC_RX_CTL_1); in awg_stop_dma()
947 val = RD4(sc, EMAC_TX_CTL_1); in awg_dma_start_tx()
1323 val = RD4(sc, EMAC_INT_STA); in awg_intr()
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhci.c432 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) in RD4() function
456 uint32_t val = RD4(sc, off & ~3); in bcm_sdhci_read_1()
477 val32 = RD4(sc, off & ~3); in bcm_sdhci_read_2()
487 return RD4(sc, off); in bcm_sdhci_read_4()
504 uint32_t val32 = RD4(sc, off & ~3); in bcm_sdhci_write_1()
532 val32 = RD4(sc, off & ~3); in bcm_sdhci_write_2()
H A Dbcm2835_sdhost.c255 val = RD4(sc, off & ~3); in RD2()
266 val = RD4(sc, off & ~3); in RD1()
276 val32 = RD4(sc, off & ~3); in WR2()
287 val32 = RD4(sc, off & ~3); in WR1()
302 RD4(sc, HC_COMMAND)); in bcm_sdhost_print_regs()
304 RD4(sc, HC_ARGUMENT)); in bcm_sdhost_print_regs()
320 RD4(sc, HC_POWER)); in bcm_sdhost_print_regs()
322 RD4(sc, HC_DEBUG)); in bcm_sdhost_print_regs()
357 dbg = RD4(sc, HC_DEBUG); in bcm_sdhost_reset()
564 cmd = RD4(sc, HC_COMMAND); in bcm_sdhost_intr()
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/freebsd/sys/arm/freescale/
H A Dfsl_ocotp.c99 RD4(struct ocotp_softc *sc, bus_size_t off) in RD4() function
172 return (RD4(ocotp_sc, off)); in fsl_ocotp_read_4()
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c66 RD4(struct ccm_softc *sc, bus_size_t off) in RD4() function
177 reg = RD4(sc, CCM_CGPR); in ccm_attach()
180 reg = RD4(sc, CCM_CLPCR); in ccm_attach()
224 reg = RD4(sc, CCM_CSCMR1); in imx_ccm_ssi_configure()
239 reg = RD4(sc, CCM_CS1CDR); in imx_ccm_ssi_configure()
253 reg = RD4(sc, CCM_CS2CDR); in imx_ccm_ssi_configure()
328 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); in imx6_ccm_sata_enable()
448 reg = RD4(sc, CCM_CCGR3); in imx_ccm_ipu_enable()
456 reg = RD4(sc, CCM_CHSCCDR); in imx_ccm_ipu_enable()
481 reg = RD4(sc, CCM_CCGR2); in imx_ccm_hdmi_enable()
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H A Dimx6_snvs.c80 RD4(struct snvs_softc *sc, bus_size_t offset) in RD4() function
106 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit) in snvs_rtc_enable()
119 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) { in snvs_gettime()
131 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
132 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
133 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
134 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
H A Dimx6_src.c57 RD4(struct src_softc *sc, bus_size_t off) in RD4() function
79 reg = RD4(src_sc, SRC_SCR); in src_reset_ipu()
84 reg = RD4(src_sc, SRC_SCR); in src_reset_ipu()
H A Dimx_epit.c133 RD4(struct epit_softc *sc, bus_size_t offset) in RD4() function
162 return (0xffffffff - RD4(sc, EPIT_CNR)); in epit_read_counter()
286 status = RD4(sc, EPIT_SR); in epit_intr()
459 while (RD4(sc, EPIT_CR) & EPIT_CR_SWR) in epit_attach()
H A Dimx_iomux.c105 RD4(struct iomux_softc *sc, bus_size_t off) in RD4() function
139 val = (RD4(sc, reg) & ~mask) | (select << shift); in iomux_configure_input()
273 return (RD4(iomux_sc, regaddr)); in imx_iomux_gpr_get()
302 val = RD4(iomux_sc, regaddr * 4); in imx_iomux_gpr_set_masked()
H A Dimx_spi.c153 RD4(struct spi_softc *sc, bus_size_t offset) in RD4() function
269 (void)RD4(sc, ECSPI_CFGREG); in spi_hw_setup()
276 while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) { in spi_empty_rxfifo()
277 sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA); in spi_empty_rxfifo()
309 status = RD4(sc, ECSPI_STATREG); in spi_intr()
359 (void)RD4(sc, ECSPI_INTREG); in spi_intr()
/freebsd/sys/arm/mv/clk/
H A Da37x0_tbg_pll.c42 #define RD4(_clk, offset, val) \ macro
61 RD4(clk, sc->tbg_bypass.offset, &val); in a37x0_tbg_pll_recalc_freq()
65 RD4(clk, sc->vcodiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
68 RD4(clk, sc->refdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
71 RD4(clk, sc->fbdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
H A Darmada38x_gen.c47 #define RD4(_clk, offset, val) \ macro
60 RD4(clk, 0, &reg); in armada38x_gen_recalc()
H A Dperiph.h53 #define RD4(_clk, offset, val) \ macro
/freebsd/sys/arm/mv/
H A Dmv_ap806_clock.c100 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
134 reg = RD4(sc, 0x400); in mv_ap806_clock_attach()
H A Dmv_ap806_gicp.c78 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
H A Dmv_ap806_sei.c102 #define RD4(sc, reg) bus_read_4((sc)->mem_res, (reg)) macro
118 tmp = RD4(sc, GICP_SEMR(sisrc->irq)); in mv_ap806_sei_isrc_mask()
287 cause = RD4(sc, GICP_SECR1); in mv_ap806_sei_intr()
289 cause |= RD4(sc, GICP_SECR0); in mv_ap806_sei_intr()
H A Dmv_cp110_clock.c134 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
302 *val = RD4(sc, addr); in mv_cp110_clock_read_4()
314 reg = RD4(sc, addr); in mv_cp110_clock_modify_4()
H A Dmv_cp110_icu.c99 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
157 reg = RD4(sc, ICU_INT_CFG(i)); in mv_cp110_icu_attach()
191 reg = RD4(sc, ICU_INT_CFG(irq_no)); in mv_cp110_icu_convert_map_data()
H A Dmv_thermal.c121 #define RD4(sc, reg) \ macro
142 reg = RD4(sc, STATUS); in mv_thermal_wait_sensor()
163 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
185 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
202 reg = RD4(sc, STATUS) & STATUS_TEMP_MASK; in mv_thermal_read_sensor()
221 reg = RD4(sc, CONTROL0); in ap806_init()
241 reg = RD4(sc, CONTROL1); in cp110_init()
247 reg = RD4(sc, CONTROL0); in cp110_init()
H A Dmvebu_pinctrl.c106 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
117 reg = RD4(sc, offset); in mv_pinctrl_configure_pin()
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_dc.c563 val = RD4(sc, DC_WINC_WIN_OPTIONS); in dc_plane_disable()
752 val = RD4(sc, DC_CMD_DISPLAY_COMMAND); in dc_crtc_prepare()
777 val = RD4(sc, DC_CMD_INT_MASK); in dc_crtc_commit()
781 val = RD4(sc, DC_CMD_INT_ENABLE); in dc_crtc_commit()
846 val = RD4(sc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
863 val = RD4(sc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
894 base = RD4(sc, DC_WINBUF_START_ADDR); in dc_finish_page_flip()
1041 val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS); in dc_cursor_set()
1045 val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS); in dc_cursor_set()
1141 val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS); in dc_hdmi_enable()
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