/qemu/accel/tcg/ |
H A D | cputlb.c | 150 static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, in tlb_window_reset() argument 153 desc->window_begin_ns = ns; in tlb_window_reset()
|
/qemu/block/ |
H A D | block-copy.c | 777 uint64_t ns = ratelimit_calculate_delay(&s->rate_limit, 0); in block_copy_dirty_clusters() local 778 if (ns > 0) { in block_copy_dirty_clusters() 782 QEMU_CLOCK_REALTIME, ns); in block_copy_dirty_clusters()
|
H A D | nvme.c | 545 NvmeIdNs ns; in nvme_identify() member 598 s->nsze = le64_to_cpu(id->ns.nsze); in nvme_identify() 599 lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)]; in nvme_identify() 601 if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) && in nvme_identify() 602 NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) == in nvme_identify() 912 unsigned long ns; in nvme_parse_filename() local 922 if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { in nvme_parse_filename()
|
H A D | trace-events | 34 …nt64_t cnt, int synced, uint64_t delay_ns) "s %p dirty count %"PRId64" synced %d delay %"PRIu64"ns"
|
/qemu/docs/about/ |
H A D | deprecated.rst | 309 ``-device nvme-ns,eui64-default=on|off`` (since 7.1) 312 In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64 314 user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.
|
/qemu/docs/devel/ |
H A D | clocks.rst | 57 representing it in units of 2 :sup:`-32` ns. The special value of 0 is used to 304 /* set initial value to 10ns / 100MHz */ 352 fprintf(stdout, "device new period is %" PRIu64 "* 2^-32 ns\n",
|
H A D | replay.rst | 105 1 ns per *real time* nanosecond. This is done by setting up a timer
|
H A D | tcg-icount.rst | 32 fixed number of ns per instruction or adjusted as execution continues
|
/qemu/docs/system/devices/ |
H A D | nvme.rst | 5 QEMU provides NVMe emulation through the ``nvme``, ``nvme-ns`` and 61 namespaces and additional features, the ``nvme-ns`` device must be used. 67 -device nvme-ns,drive=nvm-1 69 -device nvme-ns,drive=nvm-2 71 The namespaces defined by the ``nvme-ns`` device will attach to the most 118 linked to an ``nvme-subsys`` device allows additional ``nvme-ns`` parameters: 137 -device nvme-ns,drive=nvm-1,nsid=1 139 -device nvme-ns,drive=nvm-2,nsid=3,shared=off,detached=on 169 additional ``nvme-ns`` device parameters may be used to control the Copy 189 ``zoned=on`` on an ``nvme-ns`` device to configure it as a zoned namespace. [all …]
|
/qemu/docs/system/i386/ |
H A D | hyperv.rst | 64 virtual processor run time in 100ns units. This gives guest operating system an
|
/qemu/hw/adc/ |
H A D | npcm7xx_adc.c | 78 int64_t ns; in npcm7xx_adc_start_timer() local 81 ns = clock_ticks_to_ns(clk, ticks); in npcm7xx_adc_start_timer() 82 ns += now; in npcm7xx_adc_start_timer() 83 timer_mod(timer, ns); in npcm7xx_adc_start_timer()
|
/qemu/hw/arm/ |
H A D | armsse.c | 1657 int *iregion, bool *exempt, bool *ns, bool *nsc) in armsse_idau_check() argument 1667 *ns = !(region & 1); in armsse_idau_check()
|
H A D | mps2-tz.c | 1219 int *iregion, bool *exempt, bool *ns, bool *nsc) in mps2_tz_idau_check() argument 1229 *ns = !(region & 1); in mps2_tz_idau_check()
|
/qemu/hw/audio/ |
H A D | intel-hda.c | 536 int64_t ns; in intel_hda_get_wall_clk() local 538 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; in intel_hda_get_wall_clk() 539 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ in intel_hda_get_wall_clk()
|
/qemu/hw/char/ |
H A D | trace-events | 87 …t64_t wordtime) "UART%d: speed: %d, parity: %c, data bits: %d, stop bits: %d wordtime: %"PRId64"ns"
|
/qemu/hw/core/ |
H A D | nmi.c | 34 static void nmi_children(Object *o, struct do_nmi_s *ns); 38 struct do_nmi_s *ns = opaque; in do_nmi() local 44 ns->handled = true; in do_nmi() 45 nc->nmi_monitor_handler(n, ns->cpu_index, &ns->err); in do_nmi() 46 if (ns->err) { in do_nmi() 50 nmi_children(o, ns); in do_nmi() 57 object_child_foreach(o, do_nmi, ns); in nmi_children() 62 struct do_nmi_s ns = { in nmi_monitor_handle() local 68 nmi_children(object_get_root(), &ns); in nmi_monitor_handle() 69 if (ns.handled) { in nmi_monitor_handle() [all …]
|
/qemu/hw/dma/ |
H A D | pl330.c | 125 bool ns; member 151 VMSTATE_BOOL(ns, PL330Chan), 698 uint8_t ns; in pl330_dmago() local 708 ns = !!(opcode & 2); in pl330_dmago() 724 if (ch->ns && !ns) { in pl330_dmago() 729 s->ns = ns; in pl330_dmago() 899 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { in pl330_dmasev() 990 if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) { in pl330_dmawfe() 1442 res = (s->chan[chan_id].ns << 21) | in pl330_iomem_read_imp() 1466 return (s->manager.ns << 9) | (s->manager.wakeup << 4) | in pl330_iomem_read_imp() [all …]
|
/qemu/hw/intc/ |
H A D | arm_gicv3_cpuif.c | 2012 uint64_t value, int grp, bool ns) in icc_generate_sgi() argument 2060 gicv3_redist_send_sgi(ocs, grp, irq, ns); in icc_generate_sgi() 2069 bool ns = !arm_is_secure(env); in icc_sgi0r_write() local 2071 icc_generate_sgi(env, cs, value, GICV3_G0, ns); in icc_sgi0r_write() 2080 bool ns = !arm_is_secure(env); in icc_sgi1r_write() local 2082 grp = ns ? GICV3_G1NS : GICV3_G1; in icc_sgi1r_write() 2083 icc_generate_sgi(env, cs, value, grp, ns); in icc_sgi1r_write() 2094 bool ns = !arm_is_secure(env); in icc_asgi1r_write() local 2096 grp = ns ? GICV3_G1 : GICV3_G1NS; in icc_asgi1r_write() 2097 icc_generate_sgi(env, cs, value, grp, ns); in icc_asgi1r_write()
|
H A D | arm_gicv3_redist.c | 1156 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns) in gicv3_redist_send_sgi() argument 1173 if (ns && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicv3_redist_send_sgi()
|
H A D | gicv3_internal.h | 723 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
|
H A D | openpic.c | 187 static inline uint64_t ns_to_ticks(uint64_t ns) in ns_to_ticks() argument 189 return ns / OPENPIC_TIMER_NS_PER_TICK; in ns_to_ticks() 707 uint64_t ns = ticks_to_ns(val & ~TCCR_TOG); in openpic_tmr_set_tmr() local 715 if ((ns == 0) || !enabled) { in openpic_tmr_set_tmr() 723 timer_mod(tmr->qemu_timer, now + ns); /* set timer expiration. */ in openpic_tmr_set_tmr()
|
/qemu/hw/misc/ |
H A D | iotkit-secctl.c | 182 r = s->ahbexp[offset_to_ppc_idx(offset)].ns; in iotkit_secctl_s_read() 186 r = s->apb[offset_to_ppc_idx(offset)].ns; in iotkit_secctl_s_read() 192 r = s->apbexp[offset_to_ppc_idx(offset)].ns; in iotkit_secctl_s_read() 274 if (extract32(ppc->ns, i, 1)) { in iotkit_secctl_update_ppc_ap() 287 ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports); in iotkit_secctl_ppc_ns_write() 289 qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1)); in iotkit_secctl_ppc_ns_write() 613 ppc->ns = 0; in iotkit_secctl_reset_ppc() 757 VMSTATE_UINT32(ns, IoTKitSecCtlPPC),
|
/qemu/hw/misc/macio/ |
H A D | macio.c | 265 NewWorldMacIOState *ns = NEWWORLD_MACIO(d); in macio_newworld_realize() local 266 DeviceState *pic_dev = DEVICE(&ns->pic); in macio_newworld_realize() 276 sbd = SYS_BUS_DEVICE(&ns->pic); in macio_newworld_realize() 286 if (!macio_realize_ide(s, &ns->ide[0], in macio_newworld_realize() 293 if (!macio_realize_ide(s, &ns->ide[1], in macio_newworld_realize() 306 if (ns->has_pmu) { in macio_newworld_realize() 311 sbd = SYS_BUS_DEVICE(&ns->gpio); in macio_newworld_realize() 332 object_unparent(OBJECT(&ns->gpio)); in macio_newworld_realize() 352 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj); in macio_newworld_init() local 355 object_initialize_child(obj, "pic", &ns->pic, TYPE_OPENPIC); in macio_newworld_init() [all …]
|
/qemu/hw/net/ |
H A D | e1000x_common.c | 318 int64_t ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in e1000x_timestamp() local 322 int64_t timestamp = timadj + muldiv64(ns, incvalue, incperiod * 16); in e1000x_timestamp() 330 int64_t ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in e1000x_set_timinca() local 338 *timadj += (muldiv64(ns, incvalue, incperiod) - muldiv64(ns, old_incvalue, old_incperiod)) / 16; in e1000x_set_timinca()
|
H A D | trace-events | 225 …imer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns"
|