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/qemu/hw/usb/
H A Ddesc.c13 USBDescriptor *d = (void *)dest; in usb_desc_device() local
19 d->bLength = bLength; in usb_desc_device()
20 d->bDescriptorType = USB_DT_DEVICE; in usb_desc_device()
58 USBDescriptor *d = (void *)dest; in usb_desc_device_qualifier() local
84 USBDescriptor *d = (void *)dest; in usb_desc_config() local
167 USBDescriptor *d = (void *)dest; in usb_desc_iface() local
210 USBDescriptor *d = (void *)dest; in usb_desc_endpoint() local
230 d = (void *)(dest + bLength); in usb_desc_endpoint()
265 USBDescriptor *d = (void *)dest; in usb_desc_cap_usb2_ext() local
286 USBDescriptor *d = (void *)dest; in usb_desc_cap_super() local
[all …]
/qemu/hw/net/can/
H A Dcan_mioe3680_pci.c90 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja1_io_read() local
103 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja1_io_write() local
116 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja2_io_read() local
129 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja2_io_write() local
166 d->irq = pci_allocate_irq(&d->dev); in mioe3680_pci_realize()
169 can_sja_init(&d->sja_state[i], d->irq); in mioe3680_pci_realize()
173 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { in mioe3680_pci_realize()
179 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops, in mioe3680_pci_realize()
181 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops, in mioe3680_pci_realize()
186 &d->sja_io[i]); in mioe3680_pci_realize()
[all …]
H A Dcan_pcm3680_pci.c90 Pcm3680iPCIState *d = opaque; in pcm3680i_pci_sja1_io_read() local
103 Pcm3680iPCIState *d = opaque; in pcm3680i_pci_sja1_io_write() local
116 Pcm3680iPCIState *d = opaque; in pcm3680i_pci_sja2_io_read() local
129 Pcm3680iPCIState *d = opaque; in pcm3680i_pci_sja2_io_write() local
166 d->irq = pci_allocate_irq(&d->dev); in pcm3680i_pci_realize()
169 can_sja_init(&d->sja_state[i], d->irq); in pcm3680i_pci_realize()
173 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { in pcm3680i_pci_realize()
179 memory_region_init_io(&d->sja_io[0], OBJECT(d), &pcm3680i_pci_sja1_io_ops, in pcm3680i_pci_realize()
182 memory_region_init_io(&d->sja_io[1], OBJECT(d), &pcm3680i_pci_sja2_io_ops, in pcm3680i_pci_realize()
187 &d->sja_io[i]); in pcm3680i_pci_realize()
[all …]
/qemu/hw/ide/
H A Dpiix.c93 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); in bmdma_setup_bar()
108 PCIIDEState *d = PCI_IDE(dev); in piix_ide_reset() local
109 PCIDevice *pd = PCI_DEVICE(d); in piix_ide_reset()
114 ide_bus_reset(&d->bus[i]); in piix_ide_reset()
136 ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); in pci_piix_init_bus()
146 bmdma_init(&d->bus[i], &d->bmdma[i], d); in pci_piix_init_bus()
154 PCIIDEState *d = PCI_IDE(dev); in pci_piix_ide_realize() local
159 bmdma_setup_bar(d); in pci_piix_ide_realize()
171 PCIIDEState *d = PCI_IDE(dev); in pci_piix_ide_exitfn() local
175 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); in pci_piix_ide_exitfn()
[all …]
/qemu/hw/display/
H A Dvga-pci.c230 qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info); in pci_std_vga_mmio_region_init()
231 qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid)); in pci_std_vga_mmio_region_init()
267 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, in pci_std_vga_realize()
270 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); in pci_std_vga_realize()
298 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid); in pci_secondary_vga_realize()
301 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); in pci_secondary_vga_realize()
310 memory_region_del_subregion(&d->mmio, &d->mrs[0]); in pci_secondary_vga_exit()
311 memory_region_del_subregion(&d->mmio, &d->mrs[1]); in pci_secondary_vga_exit()
313 memory_region_del_subregion(&d->mmio, &d->mrs[2]); in pci_secondary_vga_exit()
316 memory_region_del_subregion(&d->mmio, &d->mrs[3]); in pci_secondary_vga_exit()
[all …]
/qemu/tests/tcg/cris/bare/
H A Dcheck_cmpr.s8 cmp.d r4,r3
14 cmp.d r4,r3
18 move.d 0xffff,r3
19 move.d -0xffff,r4
20 cmp.d r4,r3
26 cmp.d r4,r3
32 cmp.d r4,r3
48 move.d 0xffff,r3
49 move.d -0xffff,r4
78 move.d -0xff,r4
[all …]
H A Dcheck_subr.s8 sub.d r4,r3
14 sub.d r4,r3
18 move.d 0xffff,r3
19 move.d -0xffff,r4
20 sub.d r4,r3
26 sub.d r4,r3
32 sub.d r4,r3
48 move.d 0xffff,r3
49 move.d -0xffff,r4
78 move.d -0xff,r4
[all …]
H A Dcheck_orr.s8 or.d r4,r3
14 or.d r4,r3
18 move.d 0xff0f,r4
19 move.d 0xf0ff,r3
20 or.d r4,r3
25 move.d r4,r3
26 or.d r4,r3
30 move.d 0x5432f789,r4
32 or.d r4,r3
72 move.d 0x4a,r4
[all …]
H A Dcheck_addr.s8 add.d r4,r3
14 add.d r4,r3
19 move.d r4,r3
20 add.d r4,r3
25 move.d r4,r3
26 add.d r4,r3
32 add.d r4,r3
49 move.d r4,r3
55 move.d r4,r3
79 move.d r4,r3
[all …]
H A Dcheck_addxr.s8 add.d r4,r3
14 add.d r4,r3
19 move.d r4,r3
20 add.d r4,r3
25 move.d r4,r3
26 add.d r4,r3
32 add.d r4,r3
49 move.d r4,r3
55 move.d r4,r3
79 move.d r4,r3
[all …]
H A Dcheck_movemrv32.s16 move.d x,r4
24 move.d [r4+],r3
45 move.d r1,r3
67 move.d y,r4
74 move.d r0,r3
77 move.d r1,r3
78 checkr3 d
80 move.d r2,r3
90 move.d r0,r3
93 move.d r1,r3
[all …]
H A Dcheck_andr.s8 and.d r4,r3
14 and.d r4,r3
18 move.d 0xffff,r4
19 move.d r4,r3
20 and.d r4,r3
25 move.d r4,r3
26 and.d r4,r3
32 and.d r4,r3
49 move.d 0xffff,r4
78 move.d 0x5a,r4
[all …]
/qemu/tests/tcg/hexagon/
H A Dmem_noshuf.c188 int64_t d[2]; member
227 n.d[0] = ~0LL; in main()
281 n.d[0] = ~0LL; in main()
288 n.d[0] = ~0LL; in main()
292 n.d[0] = ~0LL; in main()
296 n.d[0] = ~0LL; in main()
300 n.d[0] = ~0LL; in main()
400 res64 = pred_ld_sd(false, &n.d[0], &n.d[0], in main()
406 res64 = pred_ld_sd(true, &n.d[0], &n.d[0], in main()
412 res64 = pred_ld_sd_pi(false, &n.d[0], &n.d[0], in main()
[all …]
/qemu/hw/intc/
H A Dtrace-events5 pic_set_irq(bool master, int irq, int level) "master %d irq %d level %d"
6 pic_interrupt(int irq, int intno) "irq %d intno %d"
15 apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
16 …int8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_…
27 ioapic_set_irq(int vector, int level) "vector: %d level: %d"
45 …t_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d"
77 aspeed_vic_set_irq(int irq, int level) "Enabling IRQ %d: %d"
87 …t priority_mask, int running_priority) "%s %d irq %d priority %d cpu priority mask %d cpu running …
219 nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %d priority %d"
223 …int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d derived %d (enabled: %…
[all …]
/qemu/hw/net/
H A Dvmware_utils.h32 pci_dma_read(d, addr, buf, len); in vmw_shmem_read()
39 pci_dma_write(d, addr, buf, len); in vmw_shmem_write()
51 pci_dma_read(d, addr, buf, len); in vmw_shmem_rw()
69 pci_dma_read(d, addr, &res, 1); in vmw_shmem_ld8()
78 pci_dma_write(d, addr, &value, 1); in vmw_shmem_st8()
85 pci_dma_read(d, addr, &res, 2); in vmw_shmem_ld16()
96 pci_dma_write(d, addr, &value, 2); in vmw_shmem_st16()
103 pci_dma_read(d, addr, &res, 4); in vmw_shmem_ld32()
114 pci_dma_write(d, addr, &value, 4); in vmw_shmem_st32()
121 pci_dma_read(d, addr, &res, 8); in vmw_shmem_ld64()
[all …]
/qemu/target/arm/hvf/
H A Dtrace-events1 …int32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)"
2 …nt32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d)"
5 …ort: [pc=0x%"PRIx64" va=0x%016"PRIx64" pa=0x%016"PRIx64" isv=%d iswrite=%d s1ptw=%d len=%d srt=%d]"
6 …_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d) = 0x%…
7 …t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d op1=%d crn=%d crm=%d op2=%d, val=0…
/qemu/target/arm/tcg/
H A Dgengvec64.c28 tcg_gen_xor_i64(d, d, n); in gen_rax1_i64()
34 tcg_gen_xor_vec(vece, d, d, n); in gen_rax1_vec()
59 tcg_gen_andi_i64(d, d, mask); in gen_xar8_i64()
61 tcg_gen_or_i64(d, d, t); in gen_xar8_i64()
72 tcg_gen_andi_i64(d, d, mask); in gen_xar16_i64()
74 tcg_gen_or_i64(d, d, t); in gen_xar16_i64()
80 tcg_gen_rotri_i32(d, d, sh); in gen_xar_i32()
86 tcg_gen_rotri_i64(d, d, sh); in gen_xar_i64()
142 tcg_gen_xor_i64(d, d, k); in gen_eor3_i64()
149 tcg_gen_xor_vec(vece, d, d, k); in gen_eor3_vec()
[all …]
/qemu/block/
H A Dvhdx-endian.c82 d->signature = le32_to_cpu(d->signature); in vhdx_log_desc_le_import()
83 d->file_offset = le64_to_cpu(d->file_offset); in vhdx_log_desc_le_import()
91 d->signature = cpu_to_le32(d->signature); in vhdx_log_desc_le_export()
92 d->trailing_bytes = cpu_to_le32(d->trailing_bytes); in vhdx_log_desc_le_export()
93 d->leading_bytes = cpu_to_le64(d->leading_bytes); in vhdx_log_desc_le_export()
94 d->file_offset = cpu_to_le64(d->file_offset); in vhdx_log_desc_le_export()
102 d->data_signature = le32_to_cpu(d->data_signature); in vhdx_log_data_le_import()
103 d->sequence_high = le32_to_cpu(d->sequence_high); in vhdx_log_data_le_import()
104 d->sequence_low = le32_to_cpu(d->sequence_low); in vhdx_log_data_le_import()
112 d->sequence_high = cpu_to_le32(d->sequence_high); in vhdx_log_data_le_export()
[all …]
/qemu/tests/tcg/mips/include/
H A Dwrappers_msa.h173 DO_MSA__WD__WS(NLOC_D, nloc.d)
178 DO_MSA__WD__WS(NLZC_D, nlzc.d)
183 DO_MSA__WD__WS(PCNT_D, pcnt.d)
236 DO_MSA__WD__WS_WT(BCLR_D, bclr.d)
241 DO_MSA__WD__WS_WT(BSET_D, bset.d)
246 DO_MSA__WD__WS_WT(BNEG_D, bneg.d)
295 DO_MSA__WD__WS_WT(FMAX_D, fmax.d)
380 DO_MSA__WD__WS_WT(CEQ_D, ceq.d)
709 DO_MSA__WD__WS_WT(SLL_D, sll.d)
714 DO_MSA__WD__WS_WT(SRA_D, sra.d)
[all …]
/qemu/include/hw/virtio/
H A Dvirtio-bus.h42 void (*notify)(DeviceState *d, uint16_t vector);
46 int (*load_config)(DeviceState *d, QEMUFile *f);
48 int (*load_done)(DeviceState *d, QEMUFile *f);
50 bool (*has_extra_state)(DeviceState *d);
51 bool (*query_guest_notifiers)(DeviceState *d);
70 void (*device_unplugged)(DeviceState *d);
71 int (*query_nvectors)(DeviceState *d);
77 bool (*ioeventfd_enabled)(DeviceState *d);
88 bool (*queue_enabled)(DeviceState *d, int n);
95 AddressSpace *(*get_dma_as)(DeviceState *d);
[all …]
/qemu/chardev/
H A Dchar-ringbuf.c52 return d->prod - d->cons; in DECLARE_INSTANCE_CHECKER()
65 d->cbuf[d->prod++ & (d->size - 1)] = buf[i]; in ringbuf_chr_write()
66 if (d->prod - d->cons > d->size) { in ringbuf_chr_write()
67 d->cons = d->prod - d->size; in ringbuf_chr_write()
80 for (i = 0; i < len && d->cons != d->prod; i++) { in ringbuf_chr_read()
81 buf[i] = d->cbuf[d->cons++ & (d->size - 1)]; in ringbuf_chr_read()
92 g_free(d->cbuf); in char_ringbuf_finalize()
106 if (d->size & (d->size - 1)) { in qemu_chr_open_ringbuf()
111 d->prod = 0; in qemu_chr_open_ringbuf()
112 d->cons = 0; in qemu_chr_open_ringbuf()
[all …]
/qemu/hw/pci-bridge/
H A Dcxl_upstream.c207 if (!d || !pci_is_express(d) || !d->exp.exp_cap) { in build_cdat_table()
301 pcie_port_init_reg(d); in cxl_usp_realize()
316 pcie_cap_flr_init(d); in cxl_usp_realize()
327 cxl_cstate->pdev = d; in cxl_usp_realize()
348 pcie_cap_exit(d); in cxl_usp_realize()
350 msi_uninit(d); in cxl_usp_realize()
352 pci_bridge_exitfn(d); in cxl_usp_realize()
357 pcie_aer_exit(d); in cxl_usp_exitfn()
358 pcie_cap_exit(d); in cxl_usp_exitfn()
359 msi_uninit(d); in cxl_usp_exitfn()
[all …]
/qemu/tests/tcg/s390x/
H A Dvxeh2_vs.c8 if (v1.d[0] != v2.d[0] || v1.d[1] != v2.d[1]) { \
58 const S390Vector vt_vsl = { .d[0] = 0x7FEDBB32D5AA311Dull, in main()
59 .d[1] = 0xBB65AA10912220C0ull }; in main()
60 const S390Vector vt_vsra = { .d[0] = 0xF1FE6E7399AA5466ull, in main()
62 const S390Vector vt_vsrl = { .d[0] = 0x11FE6E7399AA5466ull, in main()
64 const S390Vector vt_vsld = { .d[0] = 0x7F76EE65DD54CC43ull, in main()
66 const S390Vector vt_vsrd = { .d[0] = 0x0E060802040E000Aull, in main()
68 S390Vector vs = { .d[0] = 0x8FEEDDCCBBAA9988ull, in main()
69 .d[1] = 0x7766554433221107ull }; in main()
70 S390Vector vd = { .d[0] = 0, .d[1] = 0 }; in main()
[all …]
/qemu/tests/fp/
H A Dfp-test-log2.c19 double d; member
51 test.i, test.d, soft.i, soft.d, real.i, real.d); in compare()
75 test.d = 0.0; in main()
80 test.d = 1.0; in main()
81 real.d = 0.0; in main()
85 test.d = 2.0; in main()
86 real.d = 1.0; in main()
90 test.d = 4.0; in main()
91 real.d = 2.0; in main()
107 real.d = log2(test.d); in main()
[all …]
/qemu/tests/qtest/libqos/
H A Dvirtio-pci-modern.c40 static uint64_t get_features(QVirtioDevice *d) in get_features() argument
87 static uint64_t get_guest_features(QVirtioDevice *d) in get_guest_features() argument
109 static uint8_t get_status(QVirtioDevice *d) in get_status() argument
162 static bool get_config_isr_status(QVirtioDevice *d) in get_config_isr_status() argument
182 } while (!get_config_isr_status(d)); in wait_config_isr_status()
194 static uint16_t get_queue_size(QVirtioDevice *d) in get_queue_size() argument
284 qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset + in set_config_vector()
286 vector = qpci_io_readw(d->pdev, d->bar, d->common_cfg_offset + in set_config_vector()
297 queue_select(&d->vdev, vq_idx); in set_queue_vector()
298 qpci_io_writew(d->pdev, d->bar, d->common_cfg_offset + in set_queue_vector()
[all …]

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