| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | RegAllocPBQP.h | 151 void setNodeIdForVReg(unsigned VReg, GraphBase::NodeId NId) { in setNodeIdForVReg()
155 GraphBase::NodeId getNodeIdForVReg(unsigned VReg) const { in getNodeIdForVReg()
162 void eraseNodeIdForVReg(unsigned VReg) { in eraseNodeIdForVReg()
234 void setVReg(unsigned VReg) { this->VReg = VReg; } in setVReg()
277 unsigned VReg; variable
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| H A D | LiveIntervalUnion.h | 125 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query()
141 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init()
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| H A D | CallingConvLower.h | 166 unsigned VReg; member
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createEmptyIntervalFrom() local
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
404 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg) in MRI_NoteNewVirtualRegister()
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| H A D | LiveIntervalUnion.cpp | 150 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
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| H A D | RegAllocPBQP.cpp | 255 unsigned VReg = G.getNodeMetadata(NId).getVReg(); in apply() local
499 for (auto VReg : VRegsToAlloc) { in initializeGraph() local
569 unsigned VReg = G.getNodeMetadata(NId).getVReg(); in mapPBQPToRegAlloc() local
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| H A D | CallingConvLower.cpp | 245 unsigned VReg = MF.addLiveIn(PReg, RC); in analyzeMustTailForwardedRegisters() local
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| H A D | MachineFunction.cpp | 441 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local
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| H A D | TailDuplication.cpp | 246 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local
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| H A D | InlineSpiller.cpp | 1047 unsigned VReg =0) { in dumpMachineInstrRangeWithSlotIndex()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local
321 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
440 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
493 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitSubregNode() local
586 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/InstPrinter/ |
| H A D | NVPTXInstPrinter.cpp | 70 unsigned VReg = RegNo & 0x0FFFFFFF; in printRegName() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 2789 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
2815 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
2835 unsigned VReg; in LowerFormalArguments_64SVR4() local
2937 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4() local
3110 unsigned VReg; in LowerFormalArguments_Darwin() local
3133 unsigned VReg; in LowerFormalArguments_Darwin() local
3206 unsigned VReg; in LowerFormalArguments_Darwin() local
3229 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); in LowerFormalArguments_Darwin() local
3301 unsigned VReg; in LowerFormalArguments_Darwin() local
4640 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || in LowerCall_64SVR4() local
[all …]
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb1RegisterInfo.cpp | 464 unsigned VReg = 0; in eliminateFrameIndex() local
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| H A D | ARMISelLowering.cpp | 2965 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in StoreByValRegs() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 294 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { in removeCopies()
307 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, in canFoldIntoCSel()
2926 unsigned VReg = MI->getOperand(0).getReg(); in optimizeCondBranch() local
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| H A D | AArch64ISelLowering.cpp | 2233 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters() local
2262 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass); in saveVarArgRegisters() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 874 unsigned VReg = in LowerFormalArguments() local
879 unsigned VReg = in LowerFormalArguments() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32() local
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32() local
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64() local
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1338 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments() local
1391 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 2010 unsigned VReg = MI->getOperand(0).getReg(); in AdjustInstrPostInstrSelection() local
2193 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); in CreateLiveInRegister() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1157 unsigned VReg = getRegForValue(V); in getRegEnsuringSimpleIntegerWidening() local
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| H A D | MipsISelLowering.cpp | 856 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in addLiveIn() local
3610 unsigned VReg = addLiveIn(MF, ArgReg, RC); in copyByValRegs() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 467 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); in LowerCCCArguments() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 719 unsigned VReg = MRI.createVirtualRegister(RC); in LowerFormalArguments() local
770 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I], in LowerFormalArguments() local
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