| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vivado_ipi/axi_dmac/ |
| H A D | dest_axi_mm.v | 74 input m_axi_awready, port
|
| H A D | request_arb.v | 70 input m_axi_awready, port
|
| /dports/lang/pocl/pocl-1.8/examples/accel/rtl/platform/ |
| H A D | almaif_decoder.vhdl | 84 m_axi_awready : in std_logic; port
|
| H A D | ffaccel_toplevel.vhdl | 50 m_axi_awready : in std_logic; port
315 m_axi_awready : in std_logic; port in ffaccel_toplevel.structural.tta_accel
|
| H A D | tta-accel.vhdl | 100 m_axi_awready : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dma_master.v | 33 …input m_axi_awready, // Write address ready. This signal indicates that the slave is rea… port
|
| H A D | axi_dma_fifo.v | 44 …input m_axi_awready, // Write address ready. This signal indicates that the slave is rea… port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/ |
| H A D | rfnoc_block_axi_ram_fifo.v | 141 …input wire [ NUM_PORTS*1-1:0] m_axi_awready, // Write address ready. This signal indicat… port
|
| H A D | axi_ram_fifo.v | 120 …input wire m_axi_awready, // Write address ready. This signal indicates that … port
|
| H A D | rfnoc_block_axi_ram_fifo_tb.sv | 126 wire [ NUM_PORTS*1-1:0] m_axi_awready; net
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/ |
| H A D | rfnoc_block_replay.v | 100 input wire [ (NUM_PORTS*1)-1:0] m_axi_awready, port
|
| H A D | rfnoc_block_replay_tb.sv | 163 wire [ NUM_PORTS*1-1:0] m_axi_awready; net
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
| H A D | e320_rfnoc_image_core.v | 60 input wire [ 2-1:0] m_axi_awready, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
| H A D | n300_bist_image_core.v | 60 input wire [ 4-1:0] m_axi_awready, port
|
| H A D | n300_rfnoc_image_core.v | 60 input wire [ 4-1:0] m_axi_awready, port
|
| H A D | n320_bist_image_core.v | 78 input wire [ 4-1:0] m_axi_awready, port
|
| H A D | n310_bist_image_core.v | 78 input wire [ 4-1:0] m_axi_awready, port
|
| H A D | n320_rfnoc_image_core.v | 78 input wire [ 4-1:0] m_axi_awready, port
|
| H A D | n310_rfnoc_image_core.v | 78 input wire [ 4-1:0] m_axi_awready, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x310_rfnoc_image_core.v | 79 input wire [ 4-1:0] m_axi_awready, port
|
| H A D | x300_rfnoc_image_core.v | 79 input wire [ 4-1:0] m_axi_awready, port
|