| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dummy.v | 28 input [31:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | axil_to_ni_regport.v | 29 input [31:0] s_axi_araddr, port
|
| H A D | axil_ctrlport_master.v | 41 input wire [AXI_AWIDTH-1:0] s_axi_araddr, port
|
| H A D | axil_regport_master.v | 68 input [AWIDTH-1:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | fifo64_to_axi4lite.v | 25 input [31:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/ |
| H A D | axi_pmu.v | 37 input [31:0] s_axi_araddr, port
|
| H A D | e31x_core.v | 55 input wire [REG_AWIDTH-1:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 31 input [31:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 28 input [31:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 28 input [31:0] s_axi_araddr, port
|
| /dports/lang/pocl/pocl-1.8/examples/accel/rtl/platform/ |
| H A D | tta-axislave.vhdl | 91 s_axi_araddr : in STD_LOGIC_VECTOR (axi_addrw_g-1 downto 0); port
|
| H A D | ffaccel_toplevel.vhdl | 36 s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0); port
301 s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0); port in ffaccel_toplevel.structural.tta_accel
|
| H A D | tta-accel.vhdl | 79 s_axi_araddr : in std_logic_vector(axi_addr_width_g-1 downto 0); port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/fasec/ |
| H A D | wrc_board_fasec.vhd | 369 signal s_axi_araddr : std_logic_vector(31 downto 0); signal
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/ |
| H A D | sim_axi_ram.sv | 60 input logic [ AWIDTH-1:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport/ |
| H A D | eth_internal.v | 44 input wire [AWIDTH-1:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
| H A D | n3xx_mgt_channel_wrapper.v | 54 input wire [REG_AWIDTH-1:0] s_axi_araddr, port
|
| H A D | n3xx_core.v | 67 input [REG_AWIDTH-1:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
| H A D | n3xx_sfp_wrapper.v | 53 input [AWIDTH-1:0] s_axi_araddr, port
|
| H A D | e320_core.v | 55 input wire [REG_AWIDTH-1:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vivado_ipi/axi_dmac/ |
| H A D | axi_dmac.v | 58 input [31:0] s_axi_araddr, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x300.v | 1169 wire [31:0] s_axi_araddr; net
|