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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/
H A DPmcRegs.h46 #define B_ACPI_IO_PM1_STS_RTC BIT10
63 #define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
65 #define V_ACPI_IO_PM1_CNT_S1 BIT10
66 #define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
68 #define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
139 #define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
153 #define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10
165 #define B_TCO_IO_TCO1_STS_DMISMI BIT10
242 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsPmc.h65 #define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10
115 #define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10
132 #define B_PCH_ACPI_PM1_STS_RTC BIT10
149 #define B_PCH_ACPI_PM1_EN_RTC BIT10
164 #define V_PCH_ACPI_PM1_CNT_S1 BIT10
165 #define V_PCH_ACPI_PM1_CNT_S3 (BIT12 | BIT10)
226 #define B_PCH_SMI_STS_GPIO_SMI BIT10
304 #define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10
331 #define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10
357 #define B_PCH_TCO1_STS_DMISMI BIT10
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H A DPchRegsHsio.h15 #define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
51 #define B_PCH_HSIO_RX_DWORD8_ICFGDFETAP3_EN BIT10
69 #define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 |…
111 #define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
117 #define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
126 #define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
155 #define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN BIT10
H A DPchRegsFia.h85 #define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 | BIT9 | BIT8)
93 #define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 | BIT9 | BIT8)
101 #define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 | BIT9 | BIT8)
109 #define B_PCH_PCR_FIA_L26O (BIT11 | BIT10 | BIT9 | BIT8)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/
H A DPchRegsPmc.h66 #define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10
116 #define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10
133 #define B_PCH_ACPI_PM1_STS_RTC BIT10
150 #define B_PCH_ACPI_PM1_EN_RTC BIT10
165 #define V_PCH_ACPI_PM1_CNT_S1 BIT10
166 #define V_PCH_ACPI_PM1_CNT_S3 (BIT12 | BIT10)
227 #define B_PCH_SMI_STS_GPIO_SMI BIT10
305 #define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10
332 #define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10
358 #define B_PCH_TCO1_STS_DMISMI BIT10
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsPmc.h58 #define B_ACPI_IO_PM1_STS_RTC BIT10
74 #define B_ACPI_IO_PM1_EN_RTC BIT10
88 #define V_ACPI_IO_PM1_CNT_S1 BIT10
89 #define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
150 #define B_ACPI_IO_SMI_STS_GPIO_SMI BIT10
230 #define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
258 #define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10
284 #define B_TCO_IO_TCO1_STS_DMISMI BIT10
398 #define B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN BIT10
441 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C2 BIT10
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H A DPchRegsHsio.h45 #define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
77 #define B_HSIO_PCR_RX_DWORD8_ICFGDFETAP3_EN BIT10
93 #define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 |…
135 #define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
141 #define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
150 #define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
162 #define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN BIT10
H A DPchRegsFia.h61 #define B_PCH_FIA_PCR_L2O (BIT11 | BIT10 | BIT9 | BIT8)
69 #define B_PCH_FIA_PCR_L10O (BIT11 | BIT10 | BIT9 | BIT8)
77 #define B_PCH_FIA_PCR_L18O (BIT11 | BIT10 | BIT9 | BIT8)
85 #define B_PCH_FIA_PCR_L26O (BIT11 | BIT10 | BIT9 | BIT8)
H A DPchRegsLpc.h97 #define B_LPC_CFG_IOE_KE BIT10 ///< Keyboard Enable, Enables dec…
114 #define B_LPC_CFG_ULKMC_TRAPBY64R BIT10
153 #define B_LPC_CFG_BDE_D0 BIT10
165 #define B_LPC_CFG_FVEC0_USB_PORT_CAP (BIT11 | BIT10)
211 #define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIOS Write Report Status
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h75 #define B_PCH_LPC_COMMAND_ID BIT10 // Interrupt Disable
200 #define B_PCH_LPC_FWH_BIOS_DEC_ED0 BIT10 // D0-D8 Enable
426 #define B_PCH_ILB_DEF1_TPMPF BIT10 // usb2leg_chknbit_TPM_PF
468 #define B_PCH_ACPI_PM1_STS_RTC BIT10 // RTC Status
486 #define B_PCH_ACPI_PM1_EN_RTC BIT10 // RTC Alarm Enable Bit
523 #define B_PCH_ACPI_GPE0a_STS_BATLOW BIT10 // Battery Low Status
542 #define B_PCH_ACPI_GPE0a_EN_BATLOW BIT10 // Battery Low Enable
800 #define B_PCH_PMC_GPI_ROUT_5 (BIT11 | BIT10)
860 #define B_PCH_PMC_PSS_PG_STS_USH_VCCS BIT10 // USH VCCS
890 #define B_PCH_PMC_D3_STS_0_SCCF2 BIT10 // SCC Function 2
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H A DPchRegsSata.h67 #define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable
85 #define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status
170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /…
175 #define B_PCH_SATA_PORT2_DISABLED BIT10
191 #define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h69 #define B_PCH_LPC_COMMAND_ID BIT10 // Interrupt Disable
194 #define B_PCH_LPC_FWH_BIOS_DEC_ED0 BIT10 // D0-D8 Enable
420 #define B_PCH_ILB_DEF1_TPMPF BIT10 // usb2leg_chknbit_TPM_PF
462 #define B_PCH_ACPI_PM1_STS_RTC BIT10 // RTC Status
480 #define B_PCH_ACPI_PM1_EN_RTC BIT10 // RTC Alarm Enable Bit
517 #define B_PCH_ACPI_GPE0a_STS_BATLOW BIT10 // Battery Low Status
536 #define B_PCH_ACPI_GPE0a_EN_BATLOW BIT10 // Battery Low Enable
794 #define B_PCH_PMC_GPI_ROUT_5 (BIT11 | BIT10)
854 #define B_PCH_PMC_PSS_PG_STS_USH_VCCS BIT10 // USH VCCS
884 #define B_PCH_PMC_D3_STS_0_SCCF2 BIT10 // SCC Function 2
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H A DPchRegsSata.h61 #define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable
79 #define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status
164 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /…
169 #define B_PCH_SATA_PORT2_DISABLED BIT10
185 #define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/sysutils/edk2/edk2-edk2-stable202102/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
H A DPeCoffExtraActionLib.c112 Dr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
123 AsmWriteDr7 (BIT10); in PeCoffLoaderExtraActionCommon()
152 NewDr7 = AsmReadDr7 () | BIT10; // H/w sets bit 10, some simulators don't in PeCoffLoaderExtraActionCommon()
177 if (NewDr7 == BIT10) { in PeCoffLoaderExtraActionCommon()
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h69 #define RXSTATUS_MCF BIT10 // Frame has Multicast Addr…
84 #define TXSTATUS_NO_CA BIT10 // Carrier signal not prese…
110 #define INSTS_TDFO BIT10 // Tx Data FIFO full
144 #define MPTCTRL_PHY_RST BIT10 // Reset the PHY
205 #define MACCR_DISRTY BIT10 // Disable Transmit Retry bit
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/Library/I2CLibDxe/
H A DI2CRegs.h44 #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
57 #define I2C_INTR_START_DET BIT10
117 #define I2C_INTR_START_DET BIT10
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/Library/I2CLibPei/
H A DI2CLibPei.h42 #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
97 #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
110 #define I2C_INTR_START_DET BIT10
174 #define I2C_INTR_START_DET BIT10

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