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Searched refs:BIT7 (Results 1 – 25 of 1817) sorted by relevance

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/dports/math/primecount/primecount-7.2/lib/primesieve/src/
H A DLookupTables.cpp105 { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 },
107 { BIT1, 6, 2, 1 }, { BIT3, 4, 1, 1 }, { BIT7, 2, 1, 1 }, { BIT5, 4, 2, 1 },
109 { BIT2, 6, 2, 1 }, { BIT7, 4, 2, 1 }, { BIT5, 2, 1, 1 }, { BIT4, 4, 2, 1 },
112 { BIT4, 2, 1, 1 }, { BIT5, 4, 2, 1 }, { BIT7, 6, 4, 1 }, { BIT2, 2, 1, -7 },
114 { BIT5, 2, 1, 1 }, { BIT7, 4, 3, 1 }, { BIT3, 6, 4, 1 }, { BIT1, 2, 1, -7 },
116 { BIT7, 2, 2, 1 }, { BIT3, 4, 3, 1 }, { BIT4, 6, 5, 1 }, { BIT0, 2, 1, -7 },
118 { BIT2, 2, 2, 1 }, { BIT1, 4, 4, 1 }, { BIT0, 6, 5, 1 }, { BIT7, 2, 2, -7 },
119 { BIT7, 6, 1, 1 }, { BIT0, 4, 0, 1 }, { BIT1, 2, 0, 1 }, { BIT2, 4, 0, 1 },
125 { BIT0, 10, 2, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 2, 1, 1 },
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
[all …]
H A DEratSmall.cpp117 p[sievingPrime * 12 + 2] &= BIT7; in crossOff()
126 case 3: CHECK_FINISHED(3); *p &= BIT7; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff()
141 p[sievingPrime * 10 + 3] &= BIT7; in crossOff()
150 case 10: CHECK_FINISHED(10); *p &= BIT7; p += sievingPrime * 2 + 1; FALLTHROUGH; in crossOff()
165 p[sievingPrime * 6 + 2] &= BIT7; in crossOff()
195 p[sievingPrime * 22 + 12] &= BIT7; in crossOff()
219 p[sievingPrime * 18 + 11] &= BIT7; in crossOff()
243 p[sievingPrime * 16 + 12] &= BIT7; in crossOff()
271 p[sievingPrime * 28 + 27] &= BIT7; in crossOff()
280 case 55: CHECK_FINISHED(55); *p &= BIT7; p += sievingPrime * 2 + 2; in crossOff()
[all …]
/dports/math/primesieve/primesieve-7.7/src/
H A DLookupTables.cpp105 { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 },
107 { BIT1, 6, 2, 1 }, { BIT3, 4, 1, 1 }, { BIT7, 2, 1, 1 }, { BIT5, 4, 2, 1 },
109 { BIT2, 6, 2, 1 }, { BIT7, 4, 2, 1 }, { BIT5, 2, 1, 1 }, { BIT4, 4, 2, 1 },
112 { BIT4, 2, 1, 1 }, { BIT5, 4, 2, 1 }, { BIT7, 6, 4, 1 }, { BIT2, 2, 1, -7 },
114 { BIT5, 2, 1, 1 }, { BIT7, 4, 3, 1 }, { BIT3, 6, 4, 1 }, { BIT1, 2, 1, -7 },
116 { BIT7, 2, 2, 1 }, { BIT3, 4, 3, 1 }, { BIT4, 6, 5, 1 }, { BIT0, 2, 1, -7 },
118 { BIT2, 2, 2, 1 }, { BIT1, 4, 4, 1 }, { BIT0, 6, 5, 1 }, { BIT7, 2, 2, -7 },
119 { BIT7, 6, 1, 1 }, { BIT0, 4, 0, 1 }, { BIT1, 2, 0, 1 }, { BIT2, 4, 0, 1 },
125 { BIT0, 10, 2, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 2, 1, 1 },
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
[all …]
H A DEratSmall.cpp117 p[sievingPrime * 12 + 2] &= BIT7; in crossOff()
126 case 3: CHECK_FINISHED(3); *p &= BIT7; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff()
141 p[sievingPrime * 10 + 3] &= BIT7; in crossOff()
150 case 10: CHECK_FINISHED(10); *p &= BIT7; p += sievingPrime * 2 + 1; FALLTHROUGH; in crossOff()
165 p[sievingPrime * 6 + 2] &= BIT7; in crossOff()
195 p[sievingPrime * 22 + 12] &= BIT7; in crossOff()
219 p[sievingPrime * 18 + 11] &= BIT7; in crossOff()
243 p[sievingPrime * 16 + 12] &= BIT7; in crossOff()
271 p[sievingPrime * 28 + 27] &= BIT7; in crossOff()
280 case 55: CHECK_FINISHED(55); *p &= BIT7; p += sievingPrime * 2 + 2; in crossOff()
[all …]
/dports/mail/spambnc/usr/local/sb/dangerous/aaaworking/
H A Dcidrmatch-procmail.rc21 BIT7=128
31 { BIT7=0 }
148 * $ ${BIT7}^0
158 * $ ${BIT7}^0
169 * $ ${BIT7}^0
182 * $ ${BIT7}^0
195 * $ ${BIT7}^0
249 BIT7=128
259 { BIT7=0 }
474 BIT7=128
[all …]
/dports/mail/spambnc/usr/local/sb/functions/
H A Dcidrmatch.rc26 BIT7=128
36 { BIT7=0 }
153 * $ ${BIT7}^0
163 * $ ${BIT7}^0
174 * $ ${BIT7}^0
187 * $ ${BIT7}^0
200 * $ ${BIT7}^0
254 BIT7=128
264 { BIT7=0 }
479 BIT7=128
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/fw/fet/EnergyTrace_TSPA/
H A DVCC_Current.c355 P2OUT &= ~(BIT6+BIT7); in calibrationSetLoad()
366 if (i2cData & BIT2) { P2DIR |= BIT7; } in calibrationSetLoad()
367 else { P2DIR &= ~BIT7; } in calibrationSetLoad()
375 P2DIR |= BIT6+BIT7; in calibrationSetLoad()
386 if (i2cData & BIT2) { P2OUT |= BIT7; } in calibrationSetLoad()
387 else { P2OUT &= ~BIT7; } in calibrationSetLoad()
484 P2SEL &= ~(BIT6+BIT7); // XT1 pins to GPIO functionality in main()
485 P2SEL2 &= ~(BIT6+BIT7); in main()
487 P2DIR = BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7; in main()
510 P2SEL2 &= ~(BIT6+BIT7); in main()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h72 #define TCR_PAD_EN BIT7
91 #define EPHSR_TX_DEFR BIT7
117 #define RPCR_LS2A BIT7
136 #define CTR_LE_ENABLE BIT7
161 #define ARR_FAILED BIT7
165 #define FIFO_TEMPTY BIT7
183 #define IST_MD BIT7
194 #define RCV_RCV_DISCRD BIT7
239 #define PHYCR_COLL_TEST BIT7 // Collision test enable
266 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capabili…
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h72 #define TCR_PAD_EN BIT7
91 #define EPHSR_TX_DEFR BIT7
117 #define RPCR_LS2A BIT7
136 #define CTR_LE_ENABLE BIT7
161 #define ARR_FAILED BIT7
165 #define FIFO_TEMPTY BIT7
183 #define IST_MD BIT7
194 #define RCV_RCV_DISCRD BIT7
239 #define PHYCR_COLL_TEST BIT7 // Collision test enable
266 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capabili…
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h72 #define TCR_PAD_EN BIT7
91 #define EPHSR_TX_DEFR BIT7
117 #define RPCR_LS2A BIT7
136 #define CTR_LE_ENABLE BIT7
161 #define ARR_FAILED BIT7
165 #define FIFO_TEMPTY BIT7
183 #define IST_MD BIT7
194 #define RCV_RCV_DISCRD BIT7
239 #define PHYCR_COLL_TEST BIT7 // Collision test enable
266 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capabili…
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h72 #define TCR_PAD_EN BIT7
91 #define EPHSR_TX_DEFR BIT7
117 #define RPCR_LS2A BIT7
136 #define CTR_LE_ENABLE BIT7
161 #define ARR_FAILED BIT7
165 #define FIFO_TEMPTY BIT7
183 #define IST_MD BIT7
194 #define RCV_RCV_DISCRD BIT7
239 #define PHYCR_COLL_TEST BIT7 // Collision test enable
266 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capabili…
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h79 #define TCR_PAD_EN BIT7
98 #define EPHSR_TX_DEFR BIT7
124 #define RPCR_LS2A BIT7
143 #define CTR_LE_ENABLE BIT7
168 #define ARR_FAILED BIT7
172 #define FIFO_TEMPTY BIT7
190 #define IST_MD BIT7
201 #define RCV_RCV_DISCRD BIT7
246 #define PHYCR_COLL_TEST BIT7 // Collision test enable
273 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capabili…
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/fw/fet/FetInit/
H A DMSP_FET_init.c73 P5DIR |= (BIT3 | BIT4 | BIT5 | BIT7); // set pins initially to output direction in init_BiosPorts()
76 P5OUT &= ~BIT7; in init_BiosPorts()
88 P6DIR |= (BIT7); // set pins initially to output direction in init_BiosPorts()
101 P7SEL |= (BIT6+BIT7); // set pins to alternate port function BIT2+BIT3 in init_BiosPorts()
113 P8DIR |= (BIT0+BIT7); // set pins initially to output direction in init_BiosPorts()
/dports/devel/z88dk/z88dk/ext/cpm/
H A Dz80.c111 setflag(OVERFLOW, ((A & BIT7) != (vv & BIT7)) &&\
112 ((A & BIT7) != (tt & BIT7)));\
124 setflag(OVERFLOW, ((A & BIT7) == (vv & BIT7)) &&\
125 ((A & BIT7) != (tt & BIT7)));\
160 setflag(OVERFLOW, (i & BIT7) && !(tt & BIT7));\
165 setflag(OVERFLOW, !(i & BIT7) && (tt & BIT7));\
757 t2 = BIT7; in z80_emulator()
1063 t2 = BIT7; in z80_emulator()
1075 *r |= BIT7; in z80_emulator()
1106 t2 = BIT7; in z80_emulator()
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/hil/msp_fet/
H A DhilFpgaAccess.c63 P1DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
64 P1SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
75 P2DIR |= (BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
76 P2SEL &= ~(BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
87 P3DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
88 P3SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
99 P4DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
100 P4SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
139 P9DIR |= BIT0+BIT1+BIT2+BIT4+BIT7; // TDO is in, all others out in hil_fpga_init()
464 P8DIR |= (BIT0 + BIT7); in hil_fpga_power_up_target()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsLpc.h53 #define B_LPC_CFG_SERIRQ_CNT_SIRQEN BIT7
117 #define B_LPC_CFG_ULKMC_SMIATENDPS BIT7
156 #define B_LPC_CFG_BDE_LEG_F BIT7
169 #define B_LPC_CFG_FVEC0_SATA_RAID_CAP BIT7
196 #define B_LPC_CFG_BC_BILD BIT7 ///< BIOS Interface Lock-Down
229 #define B_PCH_IO_NMI_SC_SERR_NMI_STS BIT7
238 #define B_PCH_IO_NMI_EN_NMI_EN BIT7
265 #define B_RTC_IO_REGA_UIP BIT7
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/
H A DResetSystemLib.c76 if ((Data8 & BIT7) == BIT7) { in WaitForRTCUpdate()
77 while ((Data8 & BIT7) == BIT7) { in WaitForRTCUpdate()
83 while ((Data8 & BIT7) == 0) { in WaitForRTCUpdate()
88 while ((Data8 & BIT7) == BIT7) { in WaitForRTCUpdate()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h53 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
94 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
114 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
129 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1…
134 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
162 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x10…
163 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] …
192 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF s…
201 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF s…
211 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW in…
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h53 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
94 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
114 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
129 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1…
134 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
162 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x10…
163 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] …
192 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF s…
201 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF s…
211 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW in…
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h53 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
94 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
114 …WR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspen…
129 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1…
134 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7…
162 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x10…
163 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] …
192 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF s…
201 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF s…
211 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW in…
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h78 #define B_PCH_LPC_COMMAND_WCC BIT7 // Wait Cycle Control
95 #define B_PCH_LPC_DEV_STS_FB2B BIT7 // Fast Back to Back Capable
129 #define B_PCH_LPC_HEADTYP_MFD BIT7 // Multi-function Device
291 #define B_PCH_ILB_SERIRQ_CNT_SIRQMD BIT7 // Mode
559 #define B_PCH_SMI_EN_BIOS_RLS BIT7 // BIOS RLS
798 #define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
863 #define B_PCH_PMC_PSS_PG_STS_DFX BIT7 // DFX
893 #define B_PCH_PMC_D3_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
930 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
1024 #define B_PCH_NMI_SC_SERR_NMI_STS BIT7 // SERR# NMI Status
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h72 #define B_PCH_LPC_COMMAND_WCC BIT7 // Wait Cycle Control
89 #define B_PCH_LPC_DEV_STS_FB2B BIT7 // Fast Back to Back Capable
123 #define B_PCH_LPC_HEADTYP_MFD BIT7 // Multi-function Device
285 #define B_PCH_ILB_SERIRQ_CNT_SIRQMD BIT7 // Mode
553 #define B_PCH_SMI_EN_BIOS_RLS BIT7 // BIOS RLS
792 #define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
857 #define B_PCH_PMC_PSS_PG_STS_DFX BIT7 // DFX
887 #define B_PCH_PMC_D3_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
924 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
1018 #define B_PCH_NMI_SC_SERR_NMI_STS BIT7 // SERR# NMI Status
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h40 #define MSR_RQM BIT7 // Request For Master
48 #define DIR_DCL BIT7 // Disk change line
67 #define CMD_MT BIT7
90 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
103 #define STS1_EN BIT7 // End of Cylinder
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h40 #define MSR_RQM BIT7 // Request For Master
48 #define DIR_DCL BIT7 // Disk change line
67 #define CMD_MT BIT7
90 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
103 #define STS1_EN BIT7 // End of Cylinder
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h47 #define MSR_RQM BIT7 // Request For Master
55 #define DIR_DCL BIT7 // Disk change line
74 #define CMD_MT BIT7
97 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
110 #define STS1_EN BIT7 // End of Cylinder

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