| /dports/sysutils/u-boot-utilite/u-boot-2015.07/board/esd/cpci405/ |
| H A D | cpci405.c | 176 CPC0_CR0Reg = mfdcr(CPC0_CR0); in cpci405_version()
177 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); in cpci405_version()
186 mtdcr(CPC0_CR0, CPC0_CR0Reg); in cpci405_version()
231 CPC0_CR0Reg = mfdcr(CPC0_CR0); in misc_init_r()
232 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); in misc_init_r()
278 mtdcr(CPC0_CR0, CPC0_CR0Reg); in misc_init_r()
348 CPC0_CR0Reg = mfdcr(CPC0_CR0); in misc_init_r()
349 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); in misc_init_r()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/board/esd/cpci2dp/ |
| H A D | cpci2dp.c | 23 CPC0_CR0Reg = mfdcr(CPC0_CR0); in board_early_init_f()
24 mtdcr(CPC0_CR0, CPC0_CR0Reg | in board_early_init_f()
68 CPC0_CR0Reg = mfdcr(CPC0_CR0); in misc_init_r()
69 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); in misc_init_r()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 255 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
258 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| H A D | 4xx_uart.c | 31 #define UART0_SDR CPC0_CR0
177 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in get_serial_clock()
197 mtdcr (CPC0_CR0, reg); in get_serial_clock()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| H A D | 4xx_uart.c | 93 #define UART0_SDR CPC0_CR0
425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in serial_init_dev()
442 mtdcr (CPC0_CR0, reg); in serial_init_dev()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| H A D | 4xx_uart.c | 93 #define UART0_SDR CPC0_CR0
425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in serial_init_dev()
442 mtdcr (CPC0_CR0, reg); in serial_init_dev()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| H A D | 4xx_uart.c | 93 #define UART0_SDR CPC0_CR0
425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in serial_init_dev()
442 mtdcr (CPC0_CR0, reg); in serial_init_dev()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| H A D | 4xx_uart.c | 93 #define UART0_SDR CPC0_CR0
425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in serial_init_dev()
442 mtdcr (CPC0_CR0, reg); in serial_init_dev()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| H A D | 4xx_uart.c | 93 #define UART0_SDR CPC0_CR0
425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in serial_init_dev()
442 mtdcr (CPC0_CR0, reg); in serial_init_dev()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
| H A D | cpu.c | 272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/ |
| H A D | uart.c | 71 #define UART0_SDR CPC0_CR0
289 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; in uart_post_init()
306 mtdcr (CPC0_CR0, reg); in uart_post_init()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/include/asm/ |
| H A D | ppc440gp.h | 40 #define CPC0_CR0 (CNTRL_DCR_BASE + 0x3b) /* Control 0 register */ macro
|
| H A D | ppc405gp.h | 28 #define CPC0_CR0 0x00b1 /* chip control register 0 */ macro
|