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Searched refs:PWRCOM (Results 1 – 25 of 42) sorted by relevance

12

/dports/lang/smalltalk/smalltalk-3.2.5/opcode/
H A Dppc-opc.c1301 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1304 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1307 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1314 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1319 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1330 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1332 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1610 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
1788 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2470 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
[all …]
/dports/devel/vasm/vasm/cpus/ppc/
H A Dopcodes.h18 "tlgti", { RA, SI } ,{PWRCOM, OPTO(3,TOLGT)},
20 "tllti", { RA, SI } ,{PWRCOM, OPTO(3,TOLLT)},
22 "teqi", { RA, SI } ,{PWRCOM, OPTO(3,TOEQ)},
24 "tlgei", { RA, SI } ,{PWRCOM, OPTO(3,TOLGE)},
32 "tgti", { RA, SI } ,{PWRCOM, OPTO(3,TOGT)},
46 "ti", { TO, RA, SI } ,{PWRCOM, OP(3)},
589 "muli", { RT, RA, SI } ,{PWRCOM, OP(7)},
592 "sfi", { RT, RA, SI } ,{PWRCOM, OP(8)},
599 "cmpli", { BF, RA, UI } ,{PWRCOM, OP(10)},
604 "cmpi", { BF, RA, SI } ,{PWRCOM, OP(11)},
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1855 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2348 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2351 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2363 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2368 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2371 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2379 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2659 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2906 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4148 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
[all …]
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dppc-opc.c1874 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2402 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2405 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2417 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2422 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2425 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2433 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2713 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2960 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4204 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1855 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2348 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2351 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2363 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2368 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2371 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2379 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2659 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2906 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4148 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dppc-opc.c1922 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2450 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2453 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2465 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2470 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2473 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2481 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2761 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3008 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4252 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
[all …]
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dppc-dis.c2054 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2582 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2585 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2597 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2602 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2613 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2893 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3140 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4413 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4622 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dppc.c2058 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2590 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2593 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2605 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2610 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2621 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2901 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3148 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4428 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4637 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/
H A Dppc-opc.c1944 {"ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}},
2540 {"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}},
2543 {"sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}},
2563 {"ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}},
2571 {"lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}},
2858 {"svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}},
3112 {"ics", XL(19,150), 0xffffffff, PWRCOM, {0}},
3404 {"t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}},
4393 {"dcs", X(31,598), 0xffffffff, PWRCOM, {0}},
4413 {"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}},
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Dppc.c2061 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2593 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2596 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2608 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2613 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2624 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2904 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
3151 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
4433 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4642 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dppc-opc.c2019 {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
2625 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
2630 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
2641 {"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
2928 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
3179 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
3432 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
3464 {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
4479 {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
5406 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Dppc-opc.c2803 {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
3418 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
3423 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
3434 {"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
3721 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
3972 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
4226 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4258 {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
5316 {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
6520 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Dppc-opc.c3906 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4193 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4449 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4713 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4745 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4747 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4790 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4858 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5914 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
7304 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Dppc-opc.c3906 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4193 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4449 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4713 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4745 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4747 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4790 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4858 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5914 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
7304 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/xmon/
H A Dppc-opc.c3852 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4139 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4395 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4659 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4691 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4736 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4804 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5853 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
7254 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/xmon/
H A Dppc-opc.c3852 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4139 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4395 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4659 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4691 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4736 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4804 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5853 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
7254 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/xmon/
H A Dppc-opc.c3852 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
4139 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4395 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4659 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4691 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4736 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4804 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5853 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
7254 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Dppc-opc.c5639 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
5897 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
6273 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
6307 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
6355 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6363 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6424 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6563 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
7732 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
9980 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
[all …]

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