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Searched refs:ST_REG_FIRST (Results 1 – 25 of 72) sorted by relevance

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/dports/lang/gcc48/gcc-4.8.5/gcc/config/mips/
H A Dmips.h1625 #define ST_REG_FIRST 67 macro
1627 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1674 #define FPSW_REGNUM ST_REG_FIRST
1685 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/mips/
H A Dmips.h1620 #define ST_REG_FIRST 67 macro
1622 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1669 #define FPSW_REGNUM ST_REG_FIRST
1680 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/config/mips/
H A Dmips.h1271 #define ST_REG_FIRST 67 macro
1273 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1308 #define FPSW_REGNUM ST_REG_FIRST
1319 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
H A Dmips.c4891 && (regno - ST_REG_FIRST) % 2 == 0); in override_options()
4896 && (regno - ST_REG_FIRST) % 4 == 0); in override_options()
5092 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) in mips_conditional_register_usage()
5102 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) in mips_conditional_register_usage()
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/mips/
H A Dmips.h1669 #define ST_REG_FIRST 67 macro
1671 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1718 #define FPSW_REGNUM ST_REG_FIRST
1731 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h1842 #define ST_REG_FIRST 67 macro
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1896 #define FPSW_REGNUM ST_REG_FIRST
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc9/gcc-9.4.0/gcc/config/mips/
H A Dmips.h1897 #define ST_REG_FIRST 67 macro
1899 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1951 #define FPSW_REGNUM ST_REG_FIRST
1964 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h1842 #define ST_REG_FIRST 67 macro
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1896 #define FPSW_REGNUM ST_REG_FIRST
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/mips/
H A Dmips.h1874 #define ST_REG_FIRST 67 macro
1876 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1928 #define FPSW_REGNUM ST_REG_FIRST
1941 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/mips/
H A Dmips.h1807 #define ST_REG_FIRST 67 macro
1809 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1861 #define FPSW_REGNUM ST_REG_FIRST
1874 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/mips/
H A Dmips.h1875 #define ST_REG_FIRST 67 macro
1877 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1929 #define FPSW_REGNUM ST_REG_FIRST
1942 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/mips/
H A Dmips.h1874 #define ST_REG_FIRST 67 macro
1876 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1928 #define FPSW_REGNUM ST_REG_FIRST
1941 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/mips/
H A Dmips.h1893 #define ST_REG_FIRST 67 macro
1895 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1947 #define FPSW_REGNUM ST_REG_FIRST
1960 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h1842 #define ST_REG_FIRST 67 macro
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1896 #define FPSW_REGNUM ST_REG_FIRST
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/mips/
H A Dmips.h1842 #define ST_REG_FIRST 67 macro
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1896 #define FPSW_REGNUM ST_REG_FIRST
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/mips/
H A Dmips.h1842 #define ST_REG_FIRST 67 macro
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1896 #define FPSW_REGNUM ST_REG_FIRST
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/mips/
H A Dmips.h1875 #define ST_REG_FIRST 67 macro
1877 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1929 #define FPSW_REGNUM ST_REG_FIRST
1942 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/mips/
H A Dmips.h1897 #define ST_REG_FIRST 67 macro
1899 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1951 #define FPSW_REGNUM ST_REG_FIRST
1964 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc10/gcc-10.3.0/gcc/config/mips/
H A Dmips.h1874 #define ST_REG_FIRST 67 macro
1876 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1928 #define FPSW_REGNUM ST_REG_FIRST
1941 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc8/gcc-8.5.0/gcc/config/mips/
H A Dmips.h1842 #define ST_REG_FIRST 67 macro
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1896 #define FPSW_REGNUM ST_REG_FIRST
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc11/gcc-11.2.0/gcc/config/mips/
H A Dmips.h1875 #define ST_REG_FIRST 67 macro
1877 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1929 #define FPSW_REGNUM ST_REG_FIRST
1942 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/mips/
H A Dmips.h1897 #define ST_REG_FIRST 67 macro
1899 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1951 #define FPSW_REGNUM ST_REG_FIRST
1964 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/mips/
H A Dmips.h1807 #define ST_REG_FIRST 67 macro
1809 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1861 #define FPSW_REGNUM ST_REG_FIRST
1874 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/config/mips/
H A Dmips.h1600 #define ST_REG_FIRST 67 macro
1602 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1627 #define FPSW_REGNUM ST_REG_FIRST
1638 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/config/mips/
H A Dmips.h1600 #define ST_REG_FIRST 67 macro
1602 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1627 #define FPSW_REGNUM ST_REG_FIRST
1638 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)

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