/dports/cad/openroad/OpenROAD-2.0/src/dbSta/test/ |
H A D | write_verilog4.def | 30 - clk3 + NET clk3 + DIRECTION INPUT ; 46 - clk3 ( PIN clk3 ) ( r3 CP ) ;
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H A D | example1.def | 26 - clk3 + NET clk3 + DIRECTION INPUT ; 42 - clk3 ( PIN clk3 ) ( r3 CK ) ;
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H A D | reg1.def | 28 - clk3 + NET clk3 + DIRECTION INPUT ; 44 - clk3 ( PIN clk3 ) ( r3 CP ) ;
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H A D | read_verilog4.defok | 15 - clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ; 23 - clk3 ( PIN clk3 ) ( r3 CP ) + USE SIGNAL ;
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H A D | read_verilog1.defok | 16 - clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ; 24 - clk3 ( PIN clk3 ) ( r3 CP ) + USE SIGNAL ;
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H A D | power1.v | 5 clk3, 11 input clk3; port 22 .CK(clk3));
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H A D | example1.dspef | 24 clk3 I 71 *D_NET clk3 0.275 73 *P clk3 I 76 1 clk3 .243 79 3 clk3 r3:CK 40
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H A D | reg1.v | 1 module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; port 10 snl_ffqx1 r3 (.D(u2z), .CP(clk3), .Q(out));
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H A D | example1.v | 1 module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; port 10 DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
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H A D | read_verilog6.v | 1 module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; port 12 DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
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H A D | read_verilog4.v | 1 module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; port 10 snl_ffqx1 r3 (.D(u2z), .CP(clk3), .Q(out));
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H A D | find_clks2.def | 25 …- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 10000 3333 ) N + LAYER metal1 ( 0 0 ) (… 44 - clk3 ( PIN clk3 ) ( c3 A ) + USE SIGNAL ;
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/dports/cad/openroad/OpenROAD-2.0/src/rsz/test/ |
H A D | report_floating_nets1.v | 1 module top (in1, clk1, clk2, clk3, out); 2 input in1, clk1, clk2, clk3; port 11 DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
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H A D | reg2.def | 20 …- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 332 1000 ) N + LAYER metal1 ( 0 0 ) ( 0… 32 - clk3 ( r3 CK ) ( PIN clk3 ) + USE SIGNAL ;
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H A D | buffer_ports1.def | 20 …- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 332 1000 ) N + LAYER metal1 ( 0 0 ) ( 0… 34 - clk3 ( r3 CK ) ( PIN clk3 ) + USE SIGNAL ;
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/dports/cad/openroad/OpenROAD-2.0/src/sta/examples/ |
H A D | example1.dspef | 24 clk3 I 71 *D_NET clk3 0.275 73 *P clk3 I 76 1 clk3 .243 79 3 clk3 r3:CK 40
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H A D | example1.v | 1 module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; port 10 DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
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/dports/cad/openroad/OpenROAD-2.0/src/ifp/test/ |
H A D | init_floorplan3.defok | 20 - clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ; 28 - clk3 ( PIN clk3 ) ( r3 CK ) + USE SIGNAL ;
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H A D | init_floorplan6.defok | 20 - clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ; 28 - clk3 ( PIN clk3 ) ( r3 CK ) + USE SIGNAL ;
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H A D | init_floorplan2.defok | 20 - clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ; 28 - clk3 ( PIN clk3 ) ( r3 CK ) + USE SIGNAL ;
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H A D | reg1.v | 1 module top (in1, in2, clk1, clk2, clk3, out); 2 input in1, in2, clk1, clk2, clk3; port 10 DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out));
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H A D | reg2.v | 1 module top (in1, in2, clk1, clk2, clk3, out, reset); 2 input in1, in2, clk1, clk2, clk3, reset; port 10 sky130_fd_sc_hd__dfrtn_1 r3 (.D(u2z), .CLK_N(clk3), .Q(out), .RESET_B(reset));
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H A D | reg1.def | 20 …- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 332 1000 ) N + LAYER metal1 ( 0 0 ) ( 0… 32 - clk3 ( r3 CK ) ( PIN clk3 ) + USE SIGNAL ;
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/dports/cad/openroad/OpenROAD-2.0/test/ |
H A D | get_core_die_areas.def | 21 - clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ; 29 - clk3 ( PIN clk3 ) ( r3 CK ) + USE SIGNAL ;
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/dports/emulators/mess/mame-mame0226/src/devices/machine/ |
H A D | hd63450.h | 29 …void set_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const attotime &… in set_clocks() argument 33 m_our_clock[2] = clk3; in set_clocks() 36 …void set_burst_clocks(const attotime &clk1, const attotime &clk2, const attotime &clk3, const atto… in set_burst_clocks() argument 40 m_burst_clock[2] = clk3; in set_burst_clocks()
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