| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_demux8.v | 20 output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready, port
39 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
49 .o2_tdata(o2_tdata), .o2_tlast(o2_tlast), .o2_tvalid(o2_tvalid), .o2_tready(o2_tready),
59 .o2_tdata(o6_tdata), .o2_tlast(o6_tlast), .o2_tvalid(o6_tvalid), .o2_tready(o6_tready),
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| H A D | axi_demux4.v | 19 output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready, port
72 assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}};
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| H A D | axi_loopback.v | 45 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/ |
| H A D | chdr_xxxx_to_16sc_chain.v | 50 wire [63:0] o2_tdata; wire o2_tlast, o2_tvalid, o2_tready; net
76 .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready)
98 .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready),
105 .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready),
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| H A D | chdr_16sc_to_xxxx_chain.v | 49 wire [63:0] o2_tdata; wire o2_tlast, o2_tvalid, o2_tready; net
75 .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready)
96 .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready),
103 .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | split_stream.v | 15 output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready, port
28 assign { o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid } = {4{i_tready & i_tvalid}};
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| H A D | split_stream_fifo.v | 16 output [WIDTH-1:0] o2_tdata, output o2_tlast, output o2_tvalid, input o2_tready, port
29 ….o2_tdata(o2_tdata_int), .o2_tlast(o2_tlast_int), .o2_tvalid(o2_tvalid_int), .o2_tready(o2_tready_…
49 .o_tdata({o2_tlast, o2_tdata}), .o_tvalid(o2_tvalid), .o_tready(o2_tready),
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| H A D | complex_invert.v | 41 .o2_tdata(a_b_tdata), .o2_tlast(a_b_tlast), .o2_tvalid(a_b_tvalid), .o2_tready(a_b_tready),
78 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
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| H A D | addsub.vhd | 62 o2_tvalid : out std_ulogic; port in addsub_vhdl.rtl.split_stream_fifo
132 o2_tvalid => open,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/ |
| H A D | window.v | 93 .o2_tvalid (),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/ |
| H A D | pcie_iop2_msg_arbiter.v | 128 … .o2_tdata(e2_regi_tdata), .o2_tlast(), .o2_tvalid(e2_regi_tvalid), .o2_tready(e2_regi_tready),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/ |
| H A D | b200_core.v | 156 ….o2_tdata(u0_ctrl_tdata), .o2_tlast(u0_ctrl_tlast), .o2_tvalid(u0_ctrl_tvalid), .o2_tready(u0_ctrl…
292 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/ |
| H A D | b205_core.v | 140 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x300_pcie_int.v | 342 ….o2_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,2)), .o2_tlast(dmarx_tlast_bclk[2]), .o2_tvalid(dmarx_tval…
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| H A D | bus_int.v | 685 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/radio_200/ |
| H A D | radio_legacy.v | 314 ….o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0), …
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dma_fifo.v | 347 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0),
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