1// 2// Copyright 2013 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8 9//selectable conversion chain 10 11module chdr_16sc_to_xxxx_chain 12 #(parameter BASE = 0) 13 (input clk, input reset, 14 15 input set_stb, input [7:0] set_addr, input [31:0] set_data, 16 17 input [63:0] i_tdata, 18 input i_tlast, 19 input i_tvalid, 20 output i_tready, 21 22 output [63:0] o_tdata, 23 output o_tlast, 24 output o_tvalid, 25 input o_tready, 26 27 output [31:0] debug 28 ); 29 30 //------------------------------------------------------------------ 31 // Demux destination setting register - safe switch for demux 32 //------------------------------------------------------------------ 33 wire [1:0] demux_dst; 34 setting_reg #(.my_addr(BASE), .width(2), .at_reset(2'b00)) sr_demux_dst 35 (.clk(clk),.rst(reset), 36 .strobe(set_stb),.addr(set_addr), .in(set_data), 37 .out({demux_dst}),.changed()); 38 39 //------------------------------------------------------------------ 40 // All FIFO IO lines 41 //------------------------------------------------------------------ 42 wire [63:0] i0_tdata; wire i0_tlast, i0_tvalid, i0_tready; 43 wire [63:0] i1_tdata; wire i1_tlast, i1_tvalid, i1_tready; 44 wire [63:0] i2_tdata; wire i2_tlast, i2_tvalid, i2_tready; 45 wire [63:0] i3_tdata; wire i3_tlast, i3_tvalid, i3_tready; 46 47 wire [63:0] o0_tdata; wire o0_tlast, o0_tvalid, o0_tready; 48 wire [63:0] o1_tdata; wire o1_tlast, o1_tvalid, o1_tready; 49 wire [63:0] o2_tdata; wire o2_tlast, o2_tvalid, o2_tready; 50 wire [63:0] o3_tdata; wire o3_tlast, o3_tvalid, o3_tready; 51 52 //------------------------------------------------------------------ 53 // Instantiate converters 54 //------------------------------------------------------------------ 55 assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready}; 56 //assign {o1_tdata, o1_tlast, o1_tvalid, i1_tready} = {i1_tdata, i1_tlast, i1_tvalid, o1_tready}; 57 //assign {o2_tdata, o2_tlast, o2_tvalid, i2_tready} = {i2_tdata, i2_tlast, i2_tvalid, o2_tready}; 58 //assign {o3_tdata, o3_tlast, o3_tvalid, i3_tready} = {i3_tdata, i3_tlast, i3_tvalid, o3_tready}; 59 60 //leave path 0 for pass through 61 62 chdr_16sc_to_12sc 63 #(.BASE(89)) convert_16sc_to_12sc 64 65 (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0), 66 .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready), 67 .o_tdata(o1_tdata), .o_tlast(o1_tlast), .o_tvalid(o1_tvalid), .o_tready(o1_tready) 68 ); 69 70 chdr_16sc_to_32f 71 #(.BASE(89)) convert_16sc_to_32f 72 73 (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0), 74 .i_tdata(i2_tdata), .i_tlast(i2_tlast), .i_tvalid(i2_tvalid), .i_tready(i2_tready), 75 .o_tdata(o2_tdata), .o_tlast(o2_tlast), .o_tvalid(o2_tvalid), .o_tready(o2_tready) 76 ); 77 78 chdr_16sc_to_8sc #(.BASE(89)) convert_16sc_to_8sc 79 (.clk(clk), .reset(reset),.set_data(0), .set_stb(0), .set_addr(0), 80 .i_tdata(i3_tdata), .i_tlast(i3_tlast), .i_tvalid(i3_tvalid), .i_tready(i3_tready), 81 .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready) 82 ); 83 84 85 //------------------------------------------------------------------ 86 // Ingress and Egress muxing 87 //------------------------------------------------------------------ 88 //assign {o_tdata, o_tlast, o_tvalid, i_tready} = {i_tdata, i_tlast, i_tvalid, o_tready}; 89 ///* 90 axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_pack_chain 91 (.clk(clk), .reset(reset), .clear(1'b0), 92 .header(), .dest(demux_dst), 93 .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready), 94 .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready), 95 .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready), 96 .o2_tdata(i2_tdata), .o2_tlast(i2_tlast), .o2_tvalid(i2_tvalid), .o2_tready(i2_tready), 97 .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready)); 98 99 axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) mux_pack_chain 100 (.clk(clk), .reset(reset), .clear(1'b0), 101 .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready), 102 .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready), 103 .i2_tdata(o2_tdata), .i2_tlast(o2_tlast), .i2_tvalid(o2_tvalid), .i2_tready(o2_tready), 104 .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready), 105 .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)); 106 //*/ 107 108endmodule //chdr_16sc_to_xxxx_chain 109