| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_demux8.v | 21 output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready, port
40 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)
50 .o3_tdata(o3_tdata), .o3_tlast(o3_tlast), .o3_tvalid(o3_tvalid), .o3_tready(o3_tready)
60 .o3_tdata(o7_tdata), .o3_tlast(o7_tlast), .o3_tvalid(o7_tvalid), .o3_tready(o7_tready)
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| H A D | axi_demux4.v | 20 output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready); port
72 assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = dm_state & {4{i_tvalid_int}};
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| H A D | axi_loopback.v | 46 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/ |
| H A D | chdr_xxxx_to_16sc_chain.v | 51 wire [63:0] o3_tdata; wire o3_tlast, o3_tvalid, o3_tready; net
83 .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready)
99 .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready));
106 .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready),
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| H A D | chdr_16sc_to_xxxx_chain.v | 50 wire [63:0] o3_tdata; wire o3_tlast, o3_tvalid, o3_tready; net
81 .o_tdata(o3_tdata), .o_tlast(o3_tlast), .o_tvalid(o3_tvalid), .o_tready(o3_tready)
97 .o3_tdata(i3_tdata), .o3_tlast(i3_tlast), .o3_tvalid(i3_tvalid), .o3_tready(i3_tready));
104 .i3_tdata(o3_tdata), .i3_tlast(o3_tlast), .i3_tvalid(o3_tvalid), .i3_tready(o3_tready),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | split_stream.v | 16 output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready); port
28 assign { o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid } = {4{i_tready & i_tvalid}};
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| H A D | split_stream_fifo.v | 17 output [WIDTH-1:0] o3_tdata, output o3_tlast, output o3_tvalid, input o3_tready); port
30 ….o3_tdata(o3_tdata_int), .o3_tlast(o3_tlast_int), .o3_tvalid(o3_tvalid_int), .o3_tready(o3_tready_…
55 .o_tdata({o3_tlast, o3_tdata}), .o_tvalid(o3_tvalid), .o_tready(o3_tready),
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| H A D | complex_invert.v | 42 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0));
79 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0));
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| H A D | addsub.vhd | 66 o3_tvalid : out std_ulogic; port in addsub_vhdl.rtl.split_stream_fifo
136 o3_tvalid => open,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/ |
| H A D | window.v | 97 .o3_tvalid (),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/ |
| H A D | pcie_iop2_msg_arbiter.v | 129 … .o3_tdata(e3_regi_tdata), .o3_tlast(), .o3_tvalid(e3_regi_tvalid), .o3_tready(e3_regi_tready)
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/ |
| H A D | b200_core.v | 157 ….o3_tdata(l0_ctrl_tdata), .o3_tlast(l0_ctrl_tlast), .o3_tvalid(l0_ctrl_tvalid), .o3_tready(l0_ctrl…
293 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/ |
| H A D | b205_core.v | 141 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1)
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x300_pcie_int.v | 343 ….o3_tdata(`GET_DMA_BUS(dmarx_tdata_bclk,3)), .o3_tlast(dmarx_tlast_bclk[3]), .o3_tvalid(dmarx_tval…
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| H A D | bus_int.v | 686 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/radio_200/ |
| H A D | radio_legacy.v | 315 ….o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)); …
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dma_fifo.v | 348 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)
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