| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1244/ |
| H A D | ram_protected_sharedvar.vhd | 17 type ram_type is protected type
27 end protected ram_type;
36 type ram_type is protected body type
54 end protected body ram_type;
91 shared variable RAM : ram_type;
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1018/ |
| H A D | test.vhdl | 14 type ram_type is array (0 to 1) of std_logic_vector(7 downto 0); type
15 signal ram : ram_type := (others => (others => '0'));
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1039/ |
| H A D | ent.vhdl | 15 type ram_type is array (0 to 7) of std_logic_vector(3 downto 0); type
16 signal ram : ram_type := (others => (others => '0'));
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue50/idct.d/ |
| H A D | sync_ram.vhd | 24 type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range); type
25 signal ram : ram_type;
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue50/vector.d/ |
| H A D | sync_ram.vhd | 24 type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range); type
25 signal ram : ram_type;
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1079/ |
| H A D | test.vhdl | 22 type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0); type
23 signal ram : ram_type;
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1318/ |
| H A D | ram_blk.vhdl | 23 type ram_type is type
26 signal ram : ram_type;
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug040/ |
| H A D | extend_mask.vhd | 19 type ram_type is array (0 to 19) of std_logic_vector(20 downto 0); type
20 signal ram : ram_type := (
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| H A D | lmask.vhd | 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); type
20 signal ram : ram_type := (
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| H A D | izigzag_index.vhd | 19 type ram_type is array (0 to 63) of std_logic_vector(5 downto 0); type
20 signal ram : ram_type := (
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| H A D | bit_set_mask.vhd | 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); type
20 signal ram : ram_type := (
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| H A D | zigzag_index.vhd | 19 type ram_type is array (0 to 63) of std_logic_vector(5 downto 0); type
20 signal ram : ram_type := (
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/perf02-long/ |
| H A D | ilb_table.vhd | 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("00000000000000000000100000000000", "00000000000000000000100000101101", …
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| H A D | qq6_code6_table.vhd | 19 type ram_type is array (0 to 63) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("11111111111111111111111101111000", "11111111111111111111111101111000", …
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| H A D | qq4_code4_table.vhd | 19 type ram_type is array (0 to 15) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("00000000000000000000000000000000", "11111111111111111011000000011000", …
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| H A D | quant26bt_neg.vhd | 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("00000000000000000000000000111111", "00000000000000000000000000111110", …
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| H A D | wh_code_table.vhd | 19 type ram_type is array (0 to 3) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("00000000000000000000001100011110", "11111111111111111111111100101010", …
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| H A D | wl_code_table.vhd | 19 type ram_type is array (0 to 15) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("11111111111111111111111111000100", "00000000000000000000101111100010", …
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| H A D | decis_levl.vhd | 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("00000000000000000000000100011000", "00000000000000000000001001000000", …
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| H A D | qq2_code2_table.vhd | 19 type ram_type is array (0 to 3) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("11111111111111111110001100010000", "11111111111111111111100110110000", …
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| H A D | quant26bt_pos.vhd | 19 type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); type
20 …signal ram : ram_type := ("00000000000000000000000000111101", "00000000000000000000000000111100", …
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| /dports/devel/universal-ctags/ctags-p5.9.20211128.0/Units/parser-vhdl.r/vhdl-process.d/ |
| H A D | input.vhd | 33 type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0); type
34 signal stackbuf : ram_type;
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| H A D | expected.tags | 11 ram_type input.vhd /^ type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 …
12 stackbuf input.vhd /^ signal stackbuf : ram_type;$/;" signal architecture:StackTraceBuffer.arch…
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1021/ |
| H A D | test.vhdl | 27 type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0); type
28 signal ram : ram_type;
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| H A D | test1.vhdl | 27 type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0); type
28 signal ram : ram_type;
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