| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 913 SrcReg = TmpReg; in PPCMoveToFPReg()
991 SrcReg = TmpReg; in SelectIToFP()
1089 SrcReg = TmpReg; in SelectFPToI()
1302 Arg = TmpReg; in processCallArgs()
1314 Arg = TmpReg; in processCallArgs()
1625 SrcReg = TmpReg; in SelectRet()
1634 SrcReg = TmpReg; in SelectRet()
1869 TmpReg) in PPCMaterializeFP()
1888 .addReg(TmpReg) in PPCMaterializeFP()
1968 unsigned TmpReg = createResultReg(RC); in PPCMaterialize32BitInt() local
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| H A D | PPCFrameLowering.cpp | 1564 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
1578 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr()
1580 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr()
1581 .addReg(TmpReg, RegState::Kill) in eliminateCallFramePseudoInstr()
1585 .addReg(TmpReg); in eliminateCallFramePseudoInstr()
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| H A D | PPCISelLowering.cpp | 6848 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local
6867 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary()
6869 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); in EmitAtomicBinary()
6930 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
6988 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary()
6993 .addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
7600 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
7672 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) in EmitInstrWithCustomInserter()
7675 .addReg(TmpReg).addReg(OldVal3Reg); in EmitInstrWithCustomInserter()
7702 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) in EmitInstrWithCustomInserter()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local
293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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| H A D | Thumb1RegisterInfo.cpp | 536 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
540 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
543 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
547 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
552 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | SIRegisterInfo.cpp | 322 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj); in eliminateFrameIndex() local
324 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
326 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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| H A D | SIInstrInfo.h | 95 unsigned TmpReg,
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| H A D | SIInstrInfo.cpp | 564 RegScavenger *RS, unsigned TmpReg, in calculateLDSSpillAddress() argument
652 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) in calculateLDSSpillAddress()
656 return TmpReg; in calculateLDSSpillAddress()
2379 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local
2382 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE()
2389 .addReg(TmpReg) in splitScalar64BitBFE()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2725 unsigned TmpReg = PrevReg + 1; in parseRegisterList() local
2726 while (TmpReg <= RegNo) { in parseRegisterList()
2727 if ((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) { in parseRegisterList()
2732 PrevReg = TmpReg; in parseRegisterList()
2733 Regs.push_back(TmpReg++); in parseRegisterList()
3401 OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); in parseDirectiveCPSetup()
3416 TmpReg.clear(); in parseDirectiveCPSetup()
3421 ResTy = parseAnyRegister(TmpReg); in parseDirectiveCPSetup()
3877 OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); in ParseDirective()
3920 TmpReg.clear(); in ParseDirective()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 254 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon40936cf70111::X86AsmParser::IntelExprStateMachine
359 BaseReg = TmpReg; in onPlus()
362 IndexReg = TmpReg; in onPlus()
396 BaseReg = TmpReg; in onMinus()
399 IndexReg = TmpReg; in onMinus()
429 TmpReg = Reg; in onRegister()
485 IndexReg = TmpReg; in onInteger()
574 BaseReg = TmpReg; in onRBrac()
577 IndexReg = TmpReg; in onRBrac()
1149 unsigned TmpReg; in ParseIntelExpression() local
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
508 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
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| H A D | MipsFastISel.cpp | 229 unsigned TmpReg = createResultReg(RC); in materialize32BitInt() local
230 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
231 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 378 unsigned TmpReg = createResultReg(RC); in materializeFP() local
385 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
3977 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
3979 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
3983 Op0 = TmpReg; in emitLSL_ri()
4098 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4100 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4104 Op0 = TmpReg; in emitLSR_ri()
4207 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
4209 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1422 unsigned TmpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1423 if (TmpReg == 0) in X86SelectBranch()
1755 unsigned TmpReg = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect() local
1756 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg) in X86FastEmitCMoveSelect()
1767 unsigned TmpReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
1768 if (TmpReg == 0) in X86FastEmitCMoveSelect()
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| H A D | X86ISelLowering.cpp | 20724 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); in EmitVAARG64WithCustomInserter() local
20727 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) in EmitVAARG64WithCustomInserter()
20732 .addReg(TmpReg) in EmitVAARG64WithCustomInserter()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 3046 unsigned TmpReg = UpdReg; in expandAtomicRMW() local
3048 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); in expandAtomicRMW()
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