/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 44 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 48 if(MI->getOperand(MI->getNumOperands()-1).isImm()) in EmitAnyX86InstComments() 52 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 53 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() 56 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 59 if(MI->getOperand(MI->getNumOperands()-1).isImm()) in EmitAnyX86InstComments() 63 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 64 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() 69 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 73 if(MI->getOperand(MI->getNumOperands()-1).isImm()) in EmitAnyX86InstComments() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | R600ClauseMergePass.cpp | 76 return MI->getOperand( in getCFAluSize() 82 return MI->getOperand( in isCFAluEnabled() 124 if (LatrCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible() 125 RootCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible() 140 if (LatrCFAlu->getOperand(Mode1Idx).getImm() && in mergeIfPossible() 150 RootCFAlu->getOperand(Mode0Idx).setImm( in mergeIfPossible() 152 RootCFAlu->getOperand(KBank0Idx).setImm( in mergeIfPossible() 154 RootCFAlu->getOperand(KBank0LineIdx).setImm( in mergeIfPossible() 158 RootCFAlu->getOperand(Mode1Idx).setImm( in mergeIfPossible() 160 RootCFAlu->getOperand(KBank1Idx).setImm( in mergeIfPossible() [all …]
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H A D | R600ISelLowering.cpp | 879 N->getOperand(0), N->getOperand(1)); in ReplaceNodeResults() 888 N->getOperand(0), N->getOperand(1)); in ReplaceNodeResults() 897 N->getOperand(0), N->getOperand(1)); in ReplaceNodeResults() 906 N->getOperand(0), N->getOperand(1)); in ReplaceNodeResults() 1949 Arg->getOperand(0).getOperand(Element)); in PerformDAGCombine() 2027 N->getOperand(0), in PerformDAGCombine() 2028 N->getOperand(1), in PerformDAGCombine() 2029 N->getOperand(2), in PerformDAGCombine() 2030 N->getOperand(3), in PerformDAGCombine() 2031 N->getOperand(4), in PerformDAGCombine() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 86 switch (MI->getOperand(0).getImm()) { in printInst() 112 const MCOperand &Dst = MI->getOperand(0); in printInst() 113 const MCOperand &MO1 = MI->getOperand(1); in printInst() 114 const MCOperand &MO2 = MI->getOperand(2); in printInst() 179 MI->getOperand(3).getImm() == -4) { in printInst() 208 MI->getOperand(4).getImm() == 4) { in printInst() 300 MI->getOperand(0).isImm() && in printInst() 301 MI->getOperand(0).getImm() == 0 && in printInst() 933 if (MI->getOperand(OpNum).getReg()) { in printSBitModifierOperand() 942 O << MI->getOperand(OpNum).getImm(); in printNoHashImmediate() [all …]
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/minix/external/bsd/llvm/dist/llvm/unittests/IR/ |
H A D | MDBuilderTest.cpp | 39 Metadata *Op = MD1->getOperand(0); in TEST_F() 53 EXPECT_TRUE(mdconst::hasa<ConstantInt>(R1->getOperand(0))); in TEST_F() 67 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F() 68 EXPECT_EQ(R1->getOperand(0), R1); in TEST_F() 78 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F() 95 EXPECT_TRUE(isa<MDString>(N0->getOperand(0))); in TEST_F() 96 EXPECT_TRUE(isa<MDString>(N1->getOperand(0))); in TEST_F() 97 EXPECT_TRUE(isa<MDString>(N2->getOperand(0))); in TEST_F() 101 EXPECT_EQ(N0->getOperand(1), R); in TEST_F() 102 EXPECT_EQ(N1->getOperand(1), R); in TEST_F() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 164 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() 170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() 176 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() 177 N->getOperand(2), N->getOperand(3) }; in Select() 182 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() 183 N->getOperand(2), N->getOperand(3) }; in Select() 188 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() 189 N->getOperand(2), N->getOperand(3) }; in Select() 194 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in Select() 236 SDValue Chain = N->getOperand(0); in SelectBRIND() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 35 .addImm(MI->getOperand(1).getImm()); in lowerRILow() 40 .addImm(MI->getOperand(2).getImm()); in lowerRILow() 49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh() 54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh() 61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow() 62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow() 64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow() 65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow() 66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow() 86 .addReg(MI->getOperand(0).getReg()); in EmitInstruction() [all …]
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H A D | SystemZInstrInfo.cpp | 110 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm())); in expandRIPseudo() 152 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(), in expandZExtPseudo() 197 MI->getOperand(1).isFI() && in isSimpleMove() 827 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm()) in foldMemoryOperandImpl() 833 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm()) in foldMemoryOperandImpl() 1017 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32); in expandPostRAPseudo() 1053 MI->getOperand(1).getImm(), &MI->getOperand(2)); in getBranchInfo() 1066 MI->getOperand(2).getImm(), &MI->getOperand(3)); in getBranchInfo() 1071 MI->getOperand(2).getImm(), &MI->getOperand(3)); in getBranchInfo() 1076 MI->getOperand(2).getImm(), &MI->getOperand(3)); in getBranchInfo() [all …]
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H A D | SystemZElimCompare.cpp | 111 MI->getOperand(0).isReg() && in resultTests() 112 MI->getOperand(0).isDef() && in resultTests() 113 MI->getOperand(0).getReg() == Reg && in resultTests() 114 MI->getOperand(0).getSubReg() == SubReg) in resultTests() 130 if (MI->getOperand(1).getReg() == Reg && in resultTests() 176 if (MI->getOperand(2).getImm() != -1) in convertToBRCT() 204 .addOperand(MI->getOperand(0)) in convertToBRCT() 205 .addOperand(MI->getOperand(1)) in convertToBRCT() 292 MI->getOperand(CCDef).setIsDead(false); in adjustCCMasksForInstr() 407 .addOperand(Compare->getOperand(0)) in fuseCompareAndBranch() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 568 SDValue Src = N->getOperand(0); in SelectAddrSpaceCast() 683 SDValue N1 = N->getOperand(1); in SelectLoad() 865 SDValue Op1 = N->getOperand(1); in SelectLoadVector() 1255 Op1 = N->getOperand(2); in SelectLDGLDU() 1273 Op1 = N->getOperand(1); in SelectLDGLDU() 2052 SDValue N1 = N->getOperand(1); in SelectStore() 2279 N2 = N->getOperand(3); in SelectStoreVector() 2287 N2 = N->getOperand(5); in SelectStoreVector() 4869 Val = LHS->getOperand(0); in SelectBFE() 4960 Address = N.getOperand(0); in SelectDirectAddr() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 97 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() 98 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction() 99 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction() 126 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() 127 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction() 139 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction() 140 addImm(MI->getOperand(3).getImm()); in runOnMachineFunction() 144 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction() 160 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction() 161 addImm(MI->getOperand(2).getImm()); in runOnMachineFunction() [all …]
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H A D | HexagonNewValueJump.cpp | 149 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY() 150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY() 227 int64_t v = MI->getOperand(2).getImm(); in canCompareBeNewValueJump() 237 cmpReg1 = MI->getOperand(1).getReg(); in canCompareBeNewValueJump() 240 cmpOp2 = MI->getOperand(2).getReg(); in canCompareBeNewValueJump() 425 predReg = MI->getOperand(0).getReg(); in runOnMachineFunction() 472 MI->getOperand(0).isReg() && in runOnMachineFunction() 493 if (MI->getOperand(1).isKill()) in runOnMachineFunction() 498 if (MI->getOperand(2).isKill()) in runOnMachineFunction() 514 if (MI->getOperand(0).isReg() && in runOnMachineFunction() [all …]
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H A D | HexagonPeephole.cpp | 138 MachineOperand &Dst = MI->getOperand(0); in runOnMachineFunction() 139 MachineOperand &Src = MI->getOperand(1); in runOnMachineFunction() 157 MachineOperand &Dst = MI->getOperand(0); in runOnMachineFunction() 158 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() 159 MachineOperand &Src2 = MI->getOperand(2); in runOnMachineFunction() 174 MachineOperand &Dst = MI->getOperand(0); in runOnMachineFunction() 175 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() 176 MachineOperand &Src2 = MI->getOperand(2); in runOnMachineFunction() 189 MachineOperand &Dst = MI->getOperand(0); in runOnMachineFunction() 207 MachineOperand &Dst = MI->getOperand(0); in runOnMachineFunction() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 84 return III->getOperand(1); in FindScalarElement() 240 Builder->CreateExtractElement(BO->getOperand(0), EI.getOperand(1), in visitExtractElementInst() 243 Builder->CreateExtractElement(BO->getOperand(1), EI.getOperand(1), in visitExtractElementInst() 249 if (IE->getOperand(2) == EI.getOperand(1)) in visitExtractElementInst() 253 if (isa<Constant>(IE->getOperand(2)) && isa<Constant>(EI.getOperand(1))) { in visitExtractElementInst() 378 if (EI->getOperand(0) == LHS || EI->getOperand(0) == RHS) { in CollectSingleShuffleElements() 857 Value *LHS = SVI.getOperand(0); in visitShuffleVectorInst() 874 LHS = SVI.getOperand(0); in visitShuffleVectorInst() 875 RHS = SVI.getOperand(1); in visitShuffleVectorInst() 912 LHS = SVI.getOperand(0); in visitShuffleVectorInst() [all …]
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H A D | InstCombineShifts.cpp | 25 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms() 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() 94 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted() 478 match(Op0BO->getOperand(0), in FoldShiftByConstant() 562 Value *X = ShiftOp->getOperand(0); in FoldShiftByConstant() 697 SimplifyShlInst(I.getOperand(0), I.getOperand(1), I.hasNoSignedWrap(), in visitShl() 709 MaskedValueIsZero(I.getOperand(0), in visitShl() 738 if (Value *V = SimplifyLShrInst(I.getOperand(0), I.getOperand(1), I.isExact(), in visitLShr() 745 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitLShr() 782 if (Value *V = SimplifyAShrInst(I.getOperand(0), I.getOperand(1), I.isExact(), in visitAShr() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 979 N->getOperand(1), N->getOperand(2)); in performSETCCCombine() 1032 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine() 1599 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN() 1606 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN() 1640 Op->getOperand(1), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN() 1862 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN() 1897 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN() 1903 Op->getOperand(1), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN() 1921 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN() 1927 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 56 int64_t Value = MI->getOperand(OpNum).getImm(); in printU4ImmOperand() 63 int64_t Value = MI->getOperand(OpNum).getImm(); in printU6ImmOperand() 70 int64_t Value = MI->getOperand(OpNum).getImm(); in printS8ImmOperand() 77 int64_t Value = MI->getOperand(OpNum).getImm(); in printU8ImmOperand() 84 int64_t Value = MI->getOperand(OpNum).getImm(); in printS16ImmOperand() 91 int64_t Value = MI->getOperand(OpNum).getImm(); in printU16ImmOperand() 98 int64_t Value = MI->getOperand(OpNum).getImm(); in printS32ImmOperand() 119 const MCOperand &MO = MI->getOperand(OpNum); in printPCRelOperand() 129 printOperand(MI->getOperand(OpNum), O); in printOperand() 134 printAddress(MI->getOperand(OpNum).getReg(), in printBDAddrOperand() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 95 Base = Addr.getOperand(0); in SelectADDRri() 102 Base = Addr.getOperand(1); in SelectADDRri() 103 Offset = Addr.getOperand(0).getOperand(0); in SelectADDRri() 107 Base = Addr.getOperand(0); in SelectADDRri() 108 Offset = Addr.getOperand(1).getOperand(0); in SelectADDRri() 131 R1 = Addr.getOperand(0); in SelectADDRrr() 132 R2 = Addr.getOperand(1); in SelectADDRrr() 159 SDValue DivLHS = N->getOperand(0); in Select() 160 SDValue DivRHS = N->getOperand(1); in Select() 181 SDValue MulLHS = N->getOperand(0); in Select() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 533 Op1 = Op1.getOperand(0).getOperand(0); in SelectBitfieldInsert() 2507 SDValue Val = N->getOperand(0).getOperand(0); in Select() 2555 SDValue Ops[] = { N->getOperand(0).getOperand(0), in Select() 2556 N->getOperand(0).getOperand(1), in Select() 2597 SDValue Ops[] = { N->getOperand(0).getOperand(0), in Select() 2609 SDValue Ops[] = { N->getOperand(0).getOperand(0), in Select() 2724 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) }; in Select() 2778 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) }; in Select() 2794 N->getOperand(0), N->getOperand(4) }; in Select() 3397 Op.getOperand(0) == Op.getOperand(1)) in PeepholeCROps() [all …]
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H A D | PPCInstrInfo.cpp | 167 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr() 190 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isLoadFromStackSlot() 191 MI->getOperand(2).isFI()) { in isLoadFromStackSlot() 216 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isStoreToStackSlot() 217 MI->getOperand(2).isFI()) { in isStoreToStackSlot() 242 if (MI->getOperand(3).getImm() != 0) in commuteInstruction() 289 MI->getOperand(0).setReg(Reg2); in commuteInstruction() 292 MI->getOperand(2).setReg(Reg1); in commuteInstruction() 293 MI->getOperand(1).setReg(Reg2); in commuteInstruction() 2070 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && in processBlock() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 56 assert(Inst.getOperand(2).isImm()); in LowerLargeShift() 64 Inst.getOperand(2).setImm(Shift); in LowerLargeShift() 96 assert(InstIn.getOperand(2).isImm()); in LowerDextDins() 98 assert(InstIn.getOperand(3).isImm()); in LowerDextDins() 111 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins() 609 assert(MI.getOperand(OpNo).isReg()); in getMSAMemEncoding() 653 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding() 665 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4() 679 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1() 693 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1604 N0 == N1.getOperand(1).getOperand(0)) in visitADD() 1609 N0 == N1.getOperand(1).getOperand(1)) in visitADD() 1615 N0 == N1.getOperand(0).getOperand(1)) in visitADD() 1617 N1.getOperand(0).getOperand(0), N1.getOperand(1)); in visitADD() 1835 N0.getOperand(1).getOperand(0) == N1) in visitSUB() 1837 N0.getOperand(0), N0.getOperand(1).getOperand(1)); in visitSUB() 1841 N0.getOperand(1).getOperand(1) == N1) in visitSUB() 1843 N0.getOperand(0), N0.getOperand(1).getOperand(0)); in visitSUB() 1847 N0.getOperand(1).getOperand(1) == N1) in visitSUB() 1849 N0.getOperand(0), N0.getOperand(1).getOperand(0)); in visitSUB() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 44 unsigned char SH = MI->getOperand(2).getImm(); in printInst() 45 unsigned char MB = MI->getOperand(3).getImm(); in printInst() 67 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst() 220 int Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand() 241 if (MI->getOperand(OpNo).isImm()) in printS16ImmOperand() 242 O << (short)MI->getOperand(OpNo).getImm(); in printS16ImmOperand() 249 if (MI->getOperand(OpNo).isImm()) in printU16ImmOperand() 257 if (!MI->getOperand(OpNo).isImm()) in printBranchOperand() 268 if (!MI->getOperand(OpNo).isImm()) in printAbsBranchOperand() 321 const MCOperand &Op = MI->getOperand(OpNo); in printTLSCall() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6378 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in validateInstruction() 6735 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) in processInstruction() 7862 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction() 7898 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction() 8143 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || in processInstruction() 8168 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || in processInstruction() 8186 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in processInstruction() 8449 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction() 8488 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || in processInstruction() 8489 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && in processInstruction() [all …]
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/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 294 MergeForward ? Paired->getOperand(1) : I->getOperand(1); in mergePairedInsns() 298 if (I->getOperand(2).getImm() == in mergePairedInsns() 344 MachineOperand &MO = MI->getOperand(i); in trackRegDefsUses() 542 .addOperand(Update->getOperand(0)) in mergePreIdxUpdateInsn() 543 .addOperand(I->getOperand(0)) in mergePreIdxUpdateInsn() 544 .addOperand(I->getOperand(1)) in mergePreIdxUpdateInsn() 586 .addOperand(I->getOperand(0)) in mergePostIdxUpdateInsn() 587 .addOperand(I->getOperand(1)) in mergePostIdxUpdateInsn() 619 if (!MI->getOperand(2).isImm()) in isMatchingUpdateInsn() 800 if (!MI->getOperand(2).isImm()) { in optimizeBlock() [all …]
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