| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LivePhysRegs.cpp | 46 } else if (O->isRegMask()) in stepBackward()
82 } else if (O->isRegMask()) in stepForward()
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| H A D | DeadMachineInstructionElim.cpp | 154 } else if (MO.isRegMask()) { in runOnMachineFunction()
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| H A D | RegisterScavenging.cpp | 113 if (MO.isRegMask()) { in determineKillsAndDefs()
315 if (MO.isRegMask()) in findSurvivorReg()
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| H A D | CriticalAntiDepBreaker.cpp | 251 if (MO.isRegMask()) in ScanInstruction()
349 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) in isNewRegClobberedByRefs()
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| H A D | MachineCSE.cpp | 190 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead()
317 if (MO.isRegMask()) in PhysRegDefsReach()
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| H A D | MachineCopyPropagation.cpp | 243 if (MO.isRegMask()) in CopyPropagateBlock()
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| H A D | MachineInstrBundle.cpp | 292 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in analyzePhysReg()
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| H A D | MachineInstr.cpp | 724 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || in addOperand()
1198 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) in findRegisterDefOperandIdx()
1515 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyImplicitOps()
1916 if (MO.isRegMask()) { in setPhysRegsDeadExcept()
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| H A D | VirtRegMap.cpp | 346 if (MO.isRegMask()) in rewrite()
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| H A D | LiveIntervalAnalysis.cpp | 220 if (!MO->isRegMask()) in computeRegMasks()
917 if (MO->isRegMask()) in updateAllRanges()
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| H A D | EarlyIfConversion.cpp | 230 if (MO->isRegMask()) { in canSpeculateInstrs()
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| H A D | BranchFolding.cpp | 1601 if (MO.isRegMask()) in findHoistingInsertPosAndDeps()
1713 if (MO.isRegMask()) { in HoistCommonCodeInSuccs()
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| H A D | LiveVariables.cpp | 516 if (MO.isRegMask()) { in runOnInstr()
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| H A D | RegAllocFast.cpp | 924 if (MO.isRegMask()) { in AllocateBasicBlock()
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| H A D | MachineLICM.cpp | 431 if (MO.isRegMask()) { in ProcessMI()
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| H A D | ScheduleDAGInstrs.cpp | 1136 if (MO.isRegMask()) in fixupKills()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86VZeroUpper.cpp | 128 if (MI->isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) in hasYmmReg()
146 if (!MO.isRegMask()) in callClobbersAnyYmmReg()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 487 if (J.isRegMask()) in scavengeRegister()
543 } else if (U.isRegMask()) { in colorChain()
680 } else if (MO.isRegMask()) { in maybeKillChain()
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| H A D | AArch64LoadStoreOptimizer.cpp | 345 if (MO.isRegMask()) in trackRegDefsUses()
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| H A D | AArch64CollectLOH.cpp | 327 if (!MO.isRegMask()) in initReachingDef()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 251 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() function
485 assert(isRegMask() && "Wrong MachineOperand accessor"); in getRegMask()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb1RegisterInfo.cpp | 438 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { in saveScavengerRegister()
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| H A D | ARMBaseInstrInfo.cpp | 511 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
2498 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 578 } else if (MO.isRegMask()) { in clobbersCTR()
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| H A D | PPCInstrInfo.cpp | 1260 } else if (MO.isRegMask()) { in DefinesPredicate()
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