/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | Register.h | 20 unsigned Reg; variable 72 return Reg & MCRegister::VirtualRegFlag && !isStackSlot(Reg); in isVirtualRegister() 92 return isVirtualRegister(Reg); in isVirtual() 98 return isPhysicalRegister(Reg); in isPhysical() 104 return virtReg2Index(Reg); in virtRegIndex() 108 return Reg; 111 unsigned id() const { return Reg; } in id() 114 return MCRegister(Reg); in MCRegister() 123 return MCRegister(Reg); in asMCReg() 129 bool operator==(const Register &Other) const { return Reg == Other.Reg; } [all …]
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H A D | MachineRegisterInfo.h | 125 return MO->Contents.Reg.Next; in getNextOperandForReg() 429 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; in getVRegName() 437 VReg2Name.grow(Reg); in insertVRegByName() 438 VReg2Name[Reg] = Name.str(); in insertVRegByName() 451 def_iterator DI = def_begin(Reg); in getOneDef() 669 return VRegInfo[Reg].first; in getRegClassOrRegBank() 680 VRegInfo[Reg].first = RCOrRB; in setRegClassOrRegBank() 732 LLT getType(Register Reg) const { in getType() argument 733 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg)) in getType() 734 return VRegToType[Reg]; in getType() [all …]
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H A D | LiveVariables.h | 151 bool HandlePhysRegKill(Register Reg, MachineInstr *MI); 156 void HandlePhysRegUse(Register Reg, MachineInstr &MI); 157 void HandlePhysRegDef(Register Reg, MachineInstr *MI, 163 MachineInstr *FindLastRefOrPartRef(Register Reg); 168 MachineInstr *FindLastPartialDef(Register Reg, 211 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterKilled() 247 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterDead() 272 VarInfo &getVarInfo(Register Reg); 284 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn() 306 bool isPHIJoin(Register Reg) { return PHIJoins.test(Reg.id()); } in isPHIJoin() argument [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 60 VRegInfo[Reg].first = RC; in setRegClass() 88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass() 148 VRegInfo.grow(Reg); in createIncompleteVirtualRegister() 151 return Reg; in createIncompleteVirtualRegister() 169 return Reg; in createVirtualRegister() 179 return Reg; in cloneVirtualRegister() 193 setType(Reg, Ty); in createGenericVirtualRegister() 196 return Reg; in createGenericVirtualRegister() 208 verifyUseList(Reg); in clearVirtRegs() 438 if ((Register)LI.first == Reg || LI.second == Reg) in isLiveIn() [all …]
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H A D | AggressiveAntiDepBreaker.cpp | 83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local 84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs() 85 Regs.push_back(Reg); in GetGroupRegs() 117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive() 173 unsigned Reg = *I; in StartBlock() local 204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local 213 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe() 230 if (Reg == 0) in IsImplicitDefUse() 315 RegRefs.erase(Reg); in HandleLastUse() 570 SuperReg = Reg; in FindSuitableFreeRegisters() [all …]
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H A D | LiveVariables.cpp | 86 VirtRegInfo.grow(Reg); in getVarInfo() 87 return VirtRegInfo[Reg]; in getVarInfo() 362 if (!PhysRegUse[Reg]) { in HandlePhysRegKill() 367 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill() 424 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local 426 if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) in HandleRegMask() 445 if (PhysRegDef[Reg] || PhysRegUse[Reg]) { in HandlePhysRegDef() 653 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in runOnMachineFunction() 654 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); in runOnMachineFunction() 656 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI); in runOnMachineFunction() [all …]
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H A D | FixupStatepointCallerSaved.cpp | 122 return Reg; in performCopyPropagation() 126 return Reg; in performCopyPropagation() 141 return Reg; in performCopyPropagation() 145 return Reg; in performCopyPropagation() 150 return Reg; in performCopyPropagation() 256 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex() 366 bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; } in isCalleeSaved() argument 390 if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !is_contained(GCRegs, Reg))) in findRegistersToSpill() 420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters() 461 if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) { in insertReloads() [all …]
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H A D | CriticalAntiDepBreaker.cpp | 71 unsigned Reg = *AI; in StartBlock() local 85 unsigned Reg = *I; in StartBlock() local 89 unsigned Reg = *AI; in StartBlock() local 92 DefIndices[Reg] = ~0u; in StartBlock() 115 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local 122 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { in Observe() 186 if (Reg == 0) continue; in PrescanInstruction() 195 Classes[Reg] = NewRC; in PrescanInstruction() 312 if (Reg == 0) continue; in ScanInstruction() 322 Classes[Reg] = NewRC; in ScanInstruction() [all …]
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H A D | RegisterScavenging.cpp | 77 SI.Reg = 0; in init() 174 I.Reg = 0; in forward() 189 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg)) in forward() 228 assert((KillRegs.test(Reg) || isUnused(Reg) || in forward() 250 I.Reg = 0; in backward() 273 return Reg; in FindUnusedReg() 384 if (!MRI.isReserved(Reg) && Used.available(Reg) && in findSurvivorBackwards() 402 if (!MRI.isReserved(Reg) && Used.available(Reg)) { in findSurvivorBackwards() 490 Scavenged[SI].Reg = Reg; in spill() 585 return Reg; in scavengeRegisterBackwards() [all …]
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H A D | LivePhysRegs.cpp | 96 removeReg(Reg); in stepForward() 103 for (auto Reg : Clobbers) { in stepForward() local 106 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward() 109 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward() 111 addReg(Reg.first); in stepForward() 141 if (LiveRegs.count(Reg)) in available() 143 if (MRI.isReserved(Reg)) in available() 160 addReg(Reg); in addBlockLiveIns() 271 MBB.addLiveIn(Reg); in addLiveIns() 293 if (Reg == 0) in recomputeLivenessFlags() [all …]
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H A D | MachineInstrBundle.cpp | 156 Register Reg = MO.getReg(); in finalizeBundle() local 157 if (!Reg) in finalizeBundle() 179 Register Reg = MO.getReg(); in finalizeBundle() local 180 if (!Reg) in finalizeBundle() 184 LocalDefs.push_back(Reg); in finalizeBundle() 186 DeadDefSet.insert(Reg); in finalizeBundle() 190 KilledDefSet.erase(Reg); in finalizeBundle() 193 DeadDefSet.erase(Reg); in finalizeBundle() 210 Register Reg = LocalDefs[i]; in finalizeBundle() local 213 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); in finalizeBundle() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonVectorPrint.cpp | 74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg() 75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg() 76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg() 77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg() 113 if (isVecReg(Reg)) in getInstrVecReg() 119 if (isVecReg(Reg)) in getInstrVecReg() 125 if (isVecReg(Reg)) in getInstrVecReg() 168 unsigned Reg = 0; in runOnMachineFunction() local 183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction() 186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
H A D | MCRegister.h | 24 unsigned Reg; variable 27 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function 50 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument 51 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot() 56 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument 57 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister() 61 return Reg; 71 return Reg; in id() 77 bool operator==(const MCRegister &Other) const { return Reg == Other.Reg; } 78 bool operator!=(const MCRegister &Other) const { return Reg != Other.Reg; } [all …]
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H A D | MCRegisterInfo.h | 69 unsigned RegNo = unsigned(Reg); in contains() 253 Iter.init(Reg, DiffList); in mc_difflist_iterator() 291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator() 303 : mc_difflist_iterator(Reg, in mc_superreg_iterator() 339 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg)); in sub_and_superregs_inclusive() 598 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 615 : SRIter(Reg, MCRI) { in MCSubRegIndexIterator() 647 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 716 : RUIter(Reg, MCRI) { in MCRegUnitMaskIterator() 782 MCRegister Reg; [all …]
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/netbsd/external/gpl3/gdb/dist/sim/arm/ |
H A D | armos.c | 399 SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]); in ARMul_OSHandleSWI() 406 SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]); in ARMul_OSHandleSWI() 413 SWIopen (state, state->Reg[0], state->Reg[1]); in ARMul_OSHandleSWI() 422 state->Reg[0] = in ARMul_OSHandleSWI() 475 state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET); in ARMul_OSHandleSWI() 536 SWIrename (state, state->Reg[0], state->Reg[1]); in ARMul_OSHandleSWI() 755 state->Reg[0] = state->Reg[1]; in ARMul_OSHandleSWI() 759 SWIopen (state, state->Reg[1], state->Reg[2]); in ARMul_OSHandleSWI() 768 SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]); in ARMul_OSHandleSWI() 772 SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]); in ARMul_OSHandleSWI() [all …]
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H A D | thumbemu.c | 722 state->Reg[Rd] = state->Reg[Rn] & ~ imm8; in handle_T2_insn() 1015 state->Reg[Rd] = state->Reg[Rn] + imm12; in handle_T2_insn() 1045 state->Reg[Rd] = state->Reg[Rn] - imm12; in handle_T2_insn() 1577 state->Reg[Rd] = state->Reg[Rn] << (state->Reg[Rm] & 0xFF); in handle_T2_insn() 1594 state->Reg[Rd] = state->Reg[Rn] >> (state->Reg[Rm] & 0xFF); in handle_T2_insn() 1744 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]); in handle_T2_insn() 1752 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm]; in handle_T2_insn() 1755 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra]; in handle_T2_insn() 1860 state->Reg[Rd] += state->Reg[Rm]; in handle_v6_thumb_insn() 2538 state->Reg[14] = state->Reg[15] \ in ARMul_ThumbDecode() [all …]
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/netbsd/external/gpl3/gdb.old/dist/sim/arm/ |
H A D | armos.c | 399 SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]); in ARMul_OSHandleSWI() 406 SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]); in ARMul_OSHandleSWI() 413 SWIopen (state, state->Reg[0], state->Reg[1]); in ARMul_OSHandleSWI() 422 state->Reg[0] = in ARMul_OSHandleSWI() 475 state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET); in ARMul_OSHandleSWI() 536 SWIrename (state, state->Reg[0], state->Reg[1]); in ARMul_OSHandleSWI() 755 state->Reg[0] = state->Reg[1]; in ARMul_OSHandleSWI() 759 SWIopen (state, state->Reg[1], state->Reg[2]); in ARMul_OSHandleSWI() 768 SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]); in ARMul_OSHandleSWI() 772 SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]); in ARMul_OSHandleSWI() [all …]
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H A D | thumbemu.c | 722 state->Reg[Rd] = state->Reg[Rn] & ~ imm8; in handle_T2_insn() 1015 state->Reg[Rd] = state->Reg[Rn] + imm12; in handle_T2_insn() 1045 state->Reg[Rd] = state->Reg[Rn] - imm12; in handle_T2_insn() 1577 state->Reg[Rd] = state->Reg[Rn] << (state->Reg[Rm] & 0xFF); in handle_T2_insn() 1594 state->Reg[Rd] = state->Reg[Rn] >> (state->Reg[Rm] & 0xFF); in handle_T2_insn() 1744 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]); in handle_T2_insn() 1752 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm]; in handle_T2_insn() 1755 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra]; in handle_T2_insn() 1860 state->Reg[Rd] += state->Reg[Rm]; in handle_v6_thumb_insn() 2538 state->Reg[14] = state->Reg[15] \ in ARMul_ThumbDecode() [all …]
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/netbsd/sys/external/bsd/acpica/dist/hardware/ |
H A D | hwregs.c | 60 ACPI_GENERIC_ADDRESS *Reg, 95 ACPI_GENERIC_ADDRESS *Reg, in AcpiHwGetAccessBitWidth() argument 115 if (!Reg->BitOffset && Reg->BitWidth && in AcpiHwGetAccessBitWidth() 121 else if (Reg->AccessWidth) in AcpiHwGetAccessBitWidth() 128 Reg->BitOffset + Reg->BitWidth); in AcpiHwGetAccessBitWidth() 190 if (!Reg) in AcpiHwValidateRegister() 218 if (Reg->AccessWidth > 4) in AcpiHwValidateRegister() 228 BitWidth = ACPI_ROUND_UP (Reg->BitOffset + Reg->BitWidth, AccessWidth); in AcpiHwValidateRegister() 290 BitWidth = Reg->BitOffset + Reg->BitWidth; in AcpiHwRead() 291 BitOffset = Reg->BitOffset; in AcpiHwRead() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/ |
H A D | Target.cpp | 62 .addReg(Reg) in loadImmediate() 98 if (PPC::GPRCRegClass.contains(Reg)) in setRegTo() 99 return {loadImmediate(Reg, 32, Value)}; in setRegTo() 100 if (PPC::G8RCRegClass.contains(Reg)) in setRegTo() 101 return {loadImmediate(Reg, 64, Value)}; in setRegTo() 102 if (PPC::F4RCRegClass.contains(Reg)) in setRegTo() 108 if (PPC::VRRCRegClass.contains(Reg)) in setRegTo() 111 if (PPC::VSRCRegClass.contains(Reg)) in setRegTo() 114 .addReg(Reg) in setRegTo() 117 if (PPC::VFRCRegClass.contains(Reg)) in setRegTo() [all …]
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/netbsd/external/gpl3/gdb/dist/opcodes/ |
H A D | i386-reg.tbl | 26 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval 27 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval 70 esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval 86 rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7 305 st(1), Class=Reg|Tbyte, 0, 1, 12, 34 306 st(2), Class=Reg|Tbyte, 0, 2, 13, 35 307 st(3), Class=Reg|Tbyte, 0, 3, 14, 36 308 st(4), Class=Reg|Tbyte, 0, 4, 15, 37 309 st(5), Class=Reg|Tbyte, 0, 5, 16, 38 310 st(6), Class=Reg|Tbyte, 0, 6, 17, 39 [all …]
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/netbsd/external/gpl3/binutils.old/dist/opcodes/ |
H A D | i386-reg.tbl | 26 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval 27 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval 70 esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval 86 rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7 296 st(1), Class=Reg|Tbyte, 0, 1, 12, 34 297 st(2), Class=Reg|Tbyte, 0, 2, 13, 35 298 st(3), Class=Reg|Tbyte, 0, 3, 14, 36 299 st(4), Class=Reg|Tbyte, 0, 4, 15, 37 300 st(5), Class=Reg|Tbyte, 0, 5, 16, 38 301 st(6), Class=Reg|Tbyte, 0, 6, 17, 39 [all …]
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/netbsd/external/gpl3/gdb.old/dist/opcodes/ |
H A D | i386-reg.tbl | 26 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval 27 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval 70 esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval 86 rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7 305 st(1), Class=Reg|Tbyte, 0, 1, 12, 34 306 st(2), Class=Reg|Tbyte, 0, 2, 13, 35 307 st(3), Class=Reg|Tbyte, 0, 3, 14, 36 308 st(4), Class=Reg|Tbyte, 0, 4, 15, 37 309 st(5), Class=Reg|Tbyte, 0, 5, 16, 38 310 st(6), Class=Reg|Tbyte, 0, 6, 17, 39 [all …]
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/netbsd/external/gpl3/binutils/dist/opcodes/ |
H A D | i386-reg.tbl | 24 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval 25 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval 68 esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval 84 rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7 303 st(1), Class=Reg|Tbyte, 0, 1, 12, 34 304 st(2), Class=Reg|Tbyte, 0, 2, 13, 35 305 st(3), Class=Reg|Tbyte, 0, 3, 14, 36 306 st(4), Class=Reg|Tbyte, 0, 4, 15, 37 307 st(5), Class=Reg|Tbyte, 0, 5, 16, 38 308 st(6), Class=Reg|Tbyte, 0, 6, 17, 39 [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64TargetStreamer.h | 49 virtual void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveReg() argument 50 virtual void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegX() argument 51 virtual void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegP() argument 52 virtual void EmitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegPX() argument 54 virtual void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFReg() argument 55 virtual void EmitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegX() argument 56 virtual void EmitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegP() argument 102 void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override; 103 void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) override; 104 void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) override; [all …]
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